High-Performance NB-LDPC Decoder With Reduction of Message Exchange
This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and,...
| Autores: | , , , |
|---|---|
| Tipo de recurso: | artículo |
| Fecha de publicación: | 2016 |
| País: | España |
| Institución: | Universitat Politècnica de València (UPV) |
| Repositorio: | RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia |
| Idioma: | inglés |
| OAI Identifier: | oai:riunet.upv.es:10251/66106 |
| Acceso en línea: | https://riunet.upv.es/handle/10251/66106 |
| Access Level: | acceso abierto |
| Palabra clave: | Check node (CN) processing High rate High speed Layered schedule Non-binary low-density parity-check (NB-LDPC) VLSI design TECNOLOGIA ELECTRONICA |
| Sumario: | This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm has a negligible performance loss for high-rate codes with GF(16) and GF(32), and a performance loss smaller than 0.07 dB for high-rate codes over GF(64). In addition, a layered decoder architecture is presented and implemented on a 90-nm CMOS process for the following high-rate NB-LDPC codes: (2304, 2048) over GF(16), (837, 726) over GF(32), and (1536, 1344) over GF(64). In all cases, the achieved throughput is higher than 1 Gb/s. |
|---|