Second minimum approximation for Min-Sum decoders suitable for high-rate LDPC codes
In this paper a method to approximate the second-minimum required in the computation of the check node update of an LDPC decoder based on Min-sum algorithm is presented. The proposed approximation compensates the performance degradation caused by the utilization of a first-minimum and pseudo second-...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2019 |
| País: | España |
| Institución: | IMDEA Networks Institute |
| Repositorio: | IMDEA Networks Institute Digital Repository |
| Idioma: | inglés |
| OAI Identifier: | oai:dspace.networks.imdea.org:20.500.12761/706 |
| Acceso en línea: | http://hdl.handle.net/20.500.12761/706 https://dx.doi.org/https://doi.org/10.1007/s00034-019-01107-z |
| Access Level: | acceso abierto |
| Palabra clave: | LDPC codes Decoding Min-sum Two minimum finder High-speed architecture |
| Sumario: | In this paper a method to approximate the second-minimum required in the computation of the check node update of an LDPC decoder based on Min-sum algorithm is presented. The proposed approximation compensates the performance degradation caused by the utilization of a first-minimum and pseudo second-minimum finder instead of a true two-minimum finder in the Min-sum algorithm and improves the BER performance of high-rate LDPC codes in the error floor region. This approach applied to a complete decoder reduces the critical path and the area with independence of the selected architecture. Therefore, this method increases the maximum throughput achieved by the decoder and its area-throughput efficiency. The increase of efficiency is proportional to the degree of the check node, so the higher the code rate is, the higher the improvement in area and speed is. |
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