Tunable active inductor-based second-order all-pass filter as a time delay cell for multi-GHz operation

In this paper, a CMOS wideband second-order voltage-mode all-pass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidt...

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Detalles Bibliográficos
Autores: Aghazadeh Dafsari, Seyed Rasoul, Martínez García, Herminio|||0000-0002-7977-2577, Saberkari, Alireza, Alarcón Cot, Eduardo José|||0000-0001-7663-7153
Tipo de recurso: artículo
Fecha de publicación:2019
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/176881
Acceso en línea:https://hdl.handle.net/2117/176881
https://dx.doi.org/10.1007/s00034-019-01032-1
Access Level:acceso abierto
Palabra clave:Electronic circuits
All-pass filter
Delay
Wideband
Delay–bandwidth product
Linearity
Active inductor
Circuits electrònics
Àrees temàtiques de la UPC::Enginyeria electrònica
Descripción
Sumario:In this paper, a CMOS wideband second-order voltage-mode all-pass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidth of 5 GHz, achieving maximum delay–bandwidth product. The proposed circuit is highly linear and has an input-referred 1-dB compression point P1dB of 2 dBm. The power consumption of the proposed circuit is only 10.3 mW. On the other hand, an active inductor is employed in the all-pass filter instead of a passive RLC tank; therefore, the three passive components are eliminated, in order to tune the time delay and improve the size. In this case, even though the power consumption increases, the time delay can be controlled across an improved bandwidth of approximately 10 GHz. Moreover, the circuit demonstrates a 1-dB compression point P1dB of 18 dBm. The proposed all-pass filter is simulated in TSMC 180-nm CMOS process parameters.