Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified li...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2016 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/72621 |
| Acceso en línea: | https://hdl.handle.net/11441/72621 https://doi.org/10.1109/TED.2016.2616891 |
| Access Level: | acceso abierto |
| Palabra clave: | Tunnel transistors Steep subthreshold slope Low power Energy efficieny Low supply voltage |
| Sumario: | In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. |
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