Low interface trap density in rapid thermally annealed Al/SiNx : H/InP metal-insulator-semiconductor devices
A minimum interface trap density of 10(12) eV(-1) cm(-2) was obtained on SiNx:H/InP metalinsulator-semiconductor structures without InP surface passivation. The SiNx:H gate insulator was obtained by the electron cyclotron resonance plasma method. This insulator was deposited in a single vacuum run a...
| Autores: | , , , |
|---|---|
| Tipo de recurso: | artículo |
| Fecha de publicación: | 1999 |
| País: | España |
| Institución: | Universidad Complutense de Madrid (UCM) |
| Repositorio: | Docta Complutense |
| Idioma: | inglés |
| OAI Identifier: | oai:docta.ucm.es:20.500.14352/59284 |
| Acceso en línea: | https://hdl.handle.net/20.500.14352/59284 |
| Access Level: | acceso abierto |
| Palabra clave: | 537 Electrical-Properties Vapor-Deposition Silicon. Electricidad Electrónica (Física) 2202.03 Electricidad |
| Sumario: | A minimum interface trap density of 10(12) eV(-1) cm(-2) was obtained on SiNx:H/InP metalinsulator-semiconductor structures without InP surface passivation. The SiNx:H gate insulator was obtained by the electron cyclotron resonance plasma method. This insulator was deposited in a single vacuum run and was composed of two layers with different nitrogen-to-silicon ratios. The first layer deposited onto the InP was grown with a nitrogen-to-silicon ratio of N/Si=1.55, whereas the second one was grown with a N/Si ratio of N/Si = 1.43. After the insulator deposition, rapid thermal annealing of the devices was performed at a constant annealing time of 30 s. The interface trap density minimum value was obtained at an optimum annealing temperature of 500 degrees C. Higher annealing temperatures promote thermal degradation of the interface and a sharp increase in the trap density. |
|---|