Unpredictable bits generation based on RRAM parallel configuration
In this letter a cell with the parallel combination of two TiN/Ti/HfO2/W resistive random access memory (RRAM) devices is studied for the generation of unpredictable bits. Measurements confirm that a simultaneous parallel SET operation in which one of the two RRAMs switches to the low resistance sta...
| Autores: | , , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2018 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/127528 |
| Acceso en línea: | https://hdl.handle.net/2117/127528 https://dx.doi.org/10.1109/LED.2018.2886396 |
| Access Level: | acceso abierto |
| Palabra clave: | Electrodes Electric resistance Computer security RRAM variability PUF hardware security Elèctrodes Resistència elèctrica Seguretat informàtica Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica |
| Sumario: | In this letter a cell with the parallel combination of two TiN/Ti/HfO2/W resistive random access memory (RRAM) devices is studied for the generation of unpredictable bits. Measurements confirm that a simultaneous parallel SET operation in which one of the two RRAMs switches to the low resistance state (LRS) is an unpredictable process showing random properties for different sets of cells. Furthermore, given a device pair, the same device switches during subsequent write operations. The proposed cell is also analyzed under different current compliances and pulse widths with the same persistent behavior being observed. The features of the proposed cell, which provide data obfuscation without compromising reliability, pave the way for its application in Physical Unclonable Functions (PUFs) for hardware security purposes. |
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