Enhanced serial RRAM cell for unpredictable bit generation
In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization step), then, one of them is switched to the High Resistive State (HRS) (bit...
| Autores: | , , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2021 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/352375 |
| Acceso en línea: | https://hdl.handle.net/2117/352375 https://dx.doi.org/10.1016/j.sse.2021.108059 |
| Access Level: | acceso abierto |
| Palabra clave: | Computer security RRAM Resistive switching PUF Hardware security Unpredictable bit Seguretat informàtica Àrees temàtiques de la UPC::Informàtica |
| Sumario: | In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization step), then, one of them is switched to the High Resistive State (HRS) (bit generation step) without knowing, in advance, which one is the switching device (unmasking step). In this proposal, the larger resistance variability of HRS compared to LRS is considered to improve the masking performance of the cell (masking step). The presented experimental results are a proof-of-concept of the applicability of the proposal. |
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