Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic
© 1998 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to se...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 1998 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/373130 |
| Acceso en línea: | https://hdl.handle.net/2117/373130 https://dx.doi.org/10.1109/4.701275 |
| Access Level: | acceso abierto |
| Palabra clave: | Logic circuits Metal oxide semiconductors, Complementary Multivalued logic CMOS logic circuits Logic design Clocks Inverters Power supplies Voltage Silicon CMOS technology Cost accounting Circuits lògics Metall-òxid-semiconductors complementaris Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència::Circuits de potència |
| Sumario: | © 1998 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
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