Cita APA

Mateo Peña, D., & Rubio Sola, J. A. (1998). Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic.

Citación estilo Chicago

Mateo Peña, Diego|||0000-0001-5996-9092, y Jose Antonio|||0000-0003-1625-1472 Rubio Sola. Design and Implementation of a 5/spl Times/5 Trits Multiplier in a Quasi-adiabatic Ternary CMOS Logic. 1998.

Cita MLA

Mateo Peña, Diego|||0000-0001-5996-9092, y Jose Antonio|||0000-0003-1625-1472 Rubio Sola. Design and Implementation of a 5/spl Times/5 Trits Multiplier in a Quasi-adiabatic Ternary CMOS Logic. 1998.