Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs

Abstract: Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct...

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Detalles Bibliográficos
Autores: Núñez, Juan, Avedillo, María J.
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2017
País:España
Institución:Consejo Superior de Investigaciones Científicas (CSIC)
Repositorio:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:digital.csic.es:10261/146905
Acceso en línea:http://hdl.handle.net/10261/146905
Access Level:acceso abierto
Palabra clave:Tunnel transistors
Steep subthreshold slope
Energy efficiency
Low supply voltage
Optimal design points
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spelling Comparison of TFETs and CMOS using optimal design points for power-speed trade-offsNúñez, JuanAvedillo, María J.Tunnel transistorsSteep subthreshold slopeEnergy efficiencyLow supply voltageOptimal design pointsAbstract: Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four mosfet and FinFET transistors. The impact of logic depth, switching activity, and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.Peer reviewedInstitute of Electrical and Electronics EngineersConsejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]201720172017info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_6501Postprintinfo:eu-repo/semantics/acceptedVersionhttp://hdl.handle.net/10261/146905reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)Ingléshttps://doi.org/10.1109/TNANO.2016.2629264Síinfo:eu-repo/semantics/openAccessoai:digital.csic.es:10261/1469052026-05-22T06:33:51Z
dc.title.none.fl_str_mv Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
title Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
spellingShingle Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
Núñez, Juan
Tunnel transistors
Steep subthreshold slope
Energy efficiency
Low supply voltage
Optimal design points
title_short Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
title_full Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
title_fullStr Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
title_full_unstemmed Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
title_sort Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
dc.creator.none.fl_str_mv Núñez, Juan
Avedillo, María J.
author Núñez, Juan
author_facet Núñez, Juan
Avedillo, María J.
author_role author
author2 Avedillo, María J.
author2_role author
dc.contributor.none.fl_str_mv Consejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]
dc.subject.none.fl_str_mv Tunnel transistors
Steep subthreshold slope
Energy efficiency
Low supply voltage
Optimal design points
topic Tunnel transistors
Steep subthreshold slope
Energy efficiency
Low supply voltage
Optimal design points
description Abstract: Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four mosfet and FinFET transistors. The impact of logic depth, switching activity, and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.
publishDate 2017
dc.date.none.fl_str_mv 2017
2017
2017
dc.type.none.fl_str_mv info:eu-repo/semantics/article
http://purl.org/coar/resource_type/c_6501
Postprint
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/10261/146905
url http://hdl.handle.net/10261/146905
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv https://doi.org/10.1109/TNANO.2016.2629264
Sí
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC
instname:Consejo Superior de Investigaciones Científicas (CSIC)
instname_str Consejo Superior de Investigaciones Científicas (CSIC)
reponame_str DIGITAL.CSIC. Repositorio Institucional del CSIC
collection DIGITAL.CSIC. Repositorio Institucional del CSIC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,811543

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