Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
Abstract: Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct...
| Autores: | , |
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| Tipo de documento: | artigo |
| Estado: | Versión aceptada para publicación |
| Data de publicação: | 2017 |
| País: | España |
| Recursos: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositório: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/146905 |
| Acesso em linha: | http://hdl.handle.net/10261/146905 |
| Access Level: | Acceso aberto |
| Palavra-chave: | Tunnel transistors Steep subthreshold slope Energy efficiency Low supply voltage Optimal design points |
| Resumo: | Abstract: Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four mosfet and FinFET transistors. The impact of logic depth, switching activity, and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis. |
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