Design and fabrication of semiconductor spin qubits for quantum computing: electrical characterization
This thesis presents the design of the electrical characterization protocol of Single-Electron Transistors (SETs) for semiconductor spin qubit applications in quantum computing. SETs were manufactured in silicon using CMOS-compatible processes. Dedicated protocols for room-temperature and low-temper...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/452210 |
| Acceso en línea: | https://hdl.handle.net/2117/452210 |
| Access Level: | acceso abierto |
| Palabra clave: | Quantum computing Transistors Circuits integrats analògics CMOS Single-electron transistors SET Electrical characterization Computació quàntica Àrees temàtiques de la UPC::Física::Física de l'estat sòlid::Semiconductors |
| Sumario: | This thesis presents the design of the electrical characterization protocol of Single-Electron Transistors (SETs) for semiconductor spin qubit applications in quantum computing. SETs were manufactured in silicon using CMOS-compatible processes. Dedicated protocols for room-temperature and low-temperature characterization have been developed. The methodology includes validation of electrical contacts, source/drain activation, and channel modulation tests to verify structural integrity and transistor-like behaviour prior to cryogenic operation. Experimental results demonstrate that several devices exhibit stable modulation, validating the manufacturing process and confirming gate and barrier control. A cryogenic measurement setup was also implemented, integrating lock-in amplification and synchronized voltage control for future low-temperature experiments. This work provides a validated protocol, automated data analysis tools, and a robust foundation for further cryogenic characterization and integration of SETs into silicon-based quantum architectures. |
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