Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors

In this paper we report on the optimization of the SiNchi:H insulator, deposited by the electron cyclotron resonance (ECR) plasma method, as a dielectric for metal-insulator-semiconductor (MIS) structures built on an InP compound semiconductor. Two different MIS structures have been obtained in whic...

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Detalles Bibliográficos
Autores: Redondo, E., Martil De La Plaza, Ignacio, González Díaz, Germán, Fernández Sánchez, Paloma, Cimas Cuevas, María Rosa
Tipo de recurso: artículo
Fecha de publicación:2002
País:España
Institución:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/59103
Acceso en línea:https://hdl.handle.net/20.500.14352/59103
Access Level:acceso abierto
Palabra clave:537
Level Transient Spectroscopy
Chemical-Vapor-Deposition
Electrical-Properties
Devices
InP.
Electricidad
Electrónica (Física)
2202.03 Electricidad
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oai_identifier_str oai:docta.ucm.es:20.500.14352/59103
network_acronym_str ES
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repository_id_str
spelling Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistorsRedondo, E.Martil De La Plaza, IgnacioGonzález Díaz, GermánFernández Sánchez, PalomaCimas Cuevas, María Rosa537Level Transient SpectroscopyChemical-Vapor-DepositionElectrical-PropertiesDevicesInP.ElectricidadElectrónica (Física)2202.03 ElectricidadIn this paper we report on the optimization of the SiNchi:H insulator, deposited by the electron cyclotron resonance (ECR) plasma method, as a dielectric for metal-insulator-semiconductor (MIS) structures built on an InP compound semiconductor. Two different MIS structures have been obtained in which the minimum of the interface trap density (D-it,D-min) at the insulator/InP interface attains values of device quality. In the first structure, a Al/SiN1.5:H/SiN1.6:H/InP dual-layer insulator was obtained and optimized after rapid thermal annealing treatment at 500 degreesC for 30s. After this treatment, the value of D-it,D-min was 9 x 10(11) cm(-2) eV(-1). In the second structure, the MIS structure was Al/SiN1.6:H/InP single-layer insulator, in which the InP surface was exposed to an N-2 plasma prior to the SiN1.6:H film deposition. In this case, the value of D-it.min was 1.6 x 10(12) cm(-2) eV(-1). Both types of structures were used as gate insulators on N-channel enhanced-mode MIS field-effect transistor test devices. From the dc output characteristics of the transistors, we obtain values for the electron channel mobility in the range 1550-1600 cm(-2) V-1 s(-1). This is a confirmation of the great potential of the ECR plasma method as a simple way to obtain device quality gate structures on InP without the use of passivation processes of the InP surface prior to the deposition of the gate dielectric, thus simplifying the whole device fabrication procedure.Iop Publishing LtdUniversidad Complutense de Madrid20022002-07-0120022002-07-01journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/20.500.14352/59103reponame:Docta Complutenseinstname:Universidad Complutense de Madrid (UCM)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:docta.ucm.es:20.500.14352/591032026-06-02T12:44:21Z
dc.title.none.fl_str_mv Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors
title Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors
spellingShingle Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors
Redondo, E.
537
Level Transient Spectroscopy
Chemical-Vapor-Deposition
Electrical-Properties
Devices
InP.
Electricidad
Electrónica (Física)
2202.03 Electricidad
title_short Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors
title_full Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors
title_fullStr Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors
title_full_unstemmed Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors
title_sort Improvement of SiNx : H/InP gate structures for the fabrication of metal-insulator-semiconductor field-effect transistors
dc.creator.none.fl_str_mv Redondo, E.
Martil De La Plaza, Ignacio
González Díaz, Germán
Fernández Sánchez, Paloma
Cimas Cuevas, María Rosa
author Redondo, E.
author_facet Redondo, E.
Martil De La Plaza, Ignacio
González Díaz, Germán
Fernández Sánchez, Paloma
Cimas Cuevas, María Rosa
author_role author
author2 Martil De La Plaza, Ignacio
González Díaz, Germán
Fernández Sánchez, Paloma
Cimas Cuevas, María Rosa
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Universidad Complutense de Madrid
dc.subject.none.fl_str_mv 537
Level Transient Spectroscopy
Chemical-Vapor-Deposition
Electrical-Properties
Devices
InP.
Electricidad
Electrónica (Física)
2202.03 Electricidad
topic 537
Level Transient Spectroscopy
Chemical-Vapor-Deposition
Electrical-Properties
Devices
InP.
Electricidad
Electrónica (Física)
2202.03 Electricidad
description In this paper we report on the optimization of the SiNchi:H insulator, deposited by the electron cyclotron resonance (ECR) plasma method, as a dielectric for metal-insulator-semiconductor (MIS) structures built on an InP compound semiconductor. Two different MIS structures have been obtained in which the minimum of the interface trap density (D-it,D-min) at the insulator/InP interface attains values of device quality. In the first structure, a Al/SiN1.5:H/SiN1.6:H/InP dual-layer insulator was obtained and optimized after rapid thermal annealing treatment at 500 degreesC for 30s. After this treatment, the value of D-it,D-min was 9 x 10(11) cm(-2) eV(-1). In the second structure, the MIS structure was Al/SiN1.6:H/InP single-layer insulator, in which the InP surface was exposed to an N-2 plasma prior to the SiN1.6:H film deposition. In this case, the value of D-it.min was 1.6 x 10(12) cm(-2) eV(-1). Both types of structures were used as gate insulators on N-channel enhanced-mode MIS field-effect transistor test devices. From the dc output characteristics of the transistors, we obtain values for the electron channel mobility in the range 1550-1600 cm(-2) V-1 s(-1). This is a confirmation of the great potential of the ECR plasma method as a simple way to obtain device quality gate structures on InP without the use of passivation processes of the InP surface prior to the deposition of the gate dielectric, thus simplifying the whole device fabrication procedure.
publishDate 2002
dc.date.none.fl_str_mv 2002
2002-07-01
2002
2002-07-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/20.500.14352/59103
url https://hdl.handle.net/20.500.14352/59103
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Iop Publishing Ltd
publisher.none.fl_str_mv Iop Publishing Ltd
dc.source.none.fl_str_mv reponame:Docta Complutense
instname:Universidad Complutense de Madrid (UCM)
instname_str Universidad Complutense de Madrid (UCM)
reponame_str Docta Complutense
collection Docta Complutense
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869409334600925184
score 15,301603

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