RISC-V Hardware attack traces using runtime executed instructions dataset

Dataset containing a count of instructions executed by the proof-of-concept programs presented in the IEEE S&P 2023 paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" with side-channel attacks (spectre, spectre-v1, access-retired, zigzagger, interrupt-timing, t...

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Detalles Bibliográficos
Autores: Costa, Juan Jose, Morancho, Enric
Tipo de recurso: conjunto de datos
Fecha de publicación:2025
País:España
Institución:Consorci de Serveis Universitaris de Catalunya (CSUC)
Repositorio:CORA.Repositori de Dades de Recerca
OAI Identifier:oai:dnet:cora.rdr____::3cb170cd078fa73af081481d50a2b8f0
Acceso en línea:https://doi.org/10.34810/DATA2775
Access Level:acceso abierto
Palabra clave:Computer and Information Science
Hardware
Cybersecurity
Machine learning
Side channel attack
Spectre
Runtime
Instructions
RISC-V
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spelling RISC-V Hardware attack traces using runtime executed instructions datasetCosta, Juan JoseMorancho, EnricComputer and Information ScienceHardwareCybersecurityMachine learningSide channel attackSpectreRuntimeInstructionsRISC-VDataset containing a count of instructions executed by the proof-of-concept programs presented in the IEEE S&P 2023 paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" with side-channel attacks (spectre, spectre-v1, access-retired, zigzagger, interrupt-timing, timer-drift, page-walk, evict-reload, fence-flush, prime_probe, iflush-reload, flush-reload, flush-flush, tlb-evict, flush-fault) with a total of 20 programs; along with the data obtained for 20 benign programs/reference sets (as, b2sum, base32, base64, basicmath, bitcount, bzip2, cat, cksum, cmp, colrm, cut, dpkg, factor, ffmpeg, matrixmult, stream, stressC, stressM, gcc). All programs run on an emulated RISC-V architecture, specifically with QEMU 8.2.2 with RV64GCV architecture.CORA.Repositori de Dades de RecercaCosta Prats, Juan Jose160(RI)2025info:eu-repo/semantics/datasethttps://doi.org/10.34810/DATA2775reponame:CORA.Repositori de Dades de Recercainstname:Consorci de Serveis Universitaris de Catalunya (CSUC)Inglésinfo:eu-repo/semantics/openAccessCC0 1.0oai:dnet:cora.rdr____::3cb170cd078fa73af081481d50a2b8f02026-06-17T12:20:17Z
dc.title.none.fl_str_mv RISC-V Hardware attack traces using runtime executed instructions dataset
title RISC-V Hardware attack traces using runtime executed instructions dataset
spellingShingle RISC-V Hardware attack traces using runtime executed instructions dataset
Costa, Juan Jose
Computer and Information Science
Hardware
Cybersecurity
Machine learning
Side channel attack
Spectre
Runtime
Instructions
RISC-V
title_short RISC-V Hardware attack traces using runtime executed instructions dataset
title_full RISC-V Hardware attack traces using runtime executed instructions dataset
title_fullStr RISC-V Hardware attack traces using runtime executed instructions dataset
title_full_unstemmed RISC-V Hardware attack traces using runtime executed instructions dataset
title_sort RISC-V Hardware attack traces using runtime executed instructions dataset
dc.creator.none.fl_str_mv Costa, Juan Jose
Morancho, Enric
author Costa, Juan Jose
author_facet Costa, Juan Jose
Morancho, Enric
author_role author
author2 Morancho, Enric
author2_role author
dc.contributor.none.fl_str_mv Costa Prats, Juan Jose
160(RI)
dc.subject.none.fl_str_mv Computer and Information Science
Hardware
Cybersecurity
Machine learning
Side channel attack
Spectre
Runtime
Instructions
RISC-V
topic Computer and Information Science
Hardware
Cybersecurity
Machine learning
Side channel attack
Spectre
Runtime
Instructions
RISC-V
description Dataset containing a count of instructions executed by the proof-of-concept programs presented in the IEEE S&P 2023 paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" with side-channel attacks (spectre, spectre-v1, access-retired, zigzagger, interrupt-timing, timer-drift, page-walk, evict-reload, fence-flush, prime_probe, iflush-reload, flush-reload, flush-flush, tlb-evict, flush-fault) with a total of 20 programs; along with the data obtained for 20 benign programs/reference sets (as, b2sum, base32, base64, basicmath, bitcount, bzip2, cat, cksum, cmp, colrm, cut, dpkg, factor, ffmpeg, matrixmult, stream, stressC, stressM, gcc). All programs run on an emulated RISC-V architecture, specifically with QEMU 8.2.2 with RV64GCV architecture.
publishDate 2025
dc.date.none.fl_str_mv 2025
dc.type.none.fl_str_mv info:eu-repo/semantics/dataset
format dataset
dc.identifier.none.fl_str_mv https://doi.org/10.34810/DATA2775
url https://doi.org/10.34810/DATA2775
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
CC0 1.0
eu_rights_str_mv openAccess
rights_invalid_str_mv CC0 1.0
dc.publisher.none.fl_str_mv CORA.Repositori de Dades de Recerca
publisher.none.fl_str_mv CORA.Repositori de Dades de Recerca
dc.source.none.fl_str_mv reponame:CORA.Repositori de Dades de Recerca
instname:Consorci de Serveis Universitaris de Catalunya (CSUC)
instname_str Consorci de Serveis Universitaris de Catalunya (CSUC)
reponame_str CORA.Repositori de Dades de Recerca
collection CORA.Repositori de Dades de Recerca
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869403205941592064
score 15,81155

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