RISC-V Hardware attack traces using runtime executed instructions dataset
Dataset containing a count of instructions executed by the proof-of-concept programs presented in the IEEE S&P 2023 paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" with side-channel attacks (spectre, spectre-v1, access-retired, zigzagger, interrupt-timing, t...
| Autores: | , |
|---|---|
| Tipo de recurso: | conjunto de datos |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Consorci de Serveis Universitaris de Catalunya (CSUC) |
| Repositorio: | CORA.Repositori de Dades de Recerca |
| OAI Identifier: | oai:dnet:cora.rdr____::3cb170cd078fa73af081481d50a2b8f0 |
| Acceso en línea: | https://doi.org/10.34810/DATA2775 |
| Access Level: | acceso abierto |
| Palabra clave: | Computer and Information Science Hardware Cybersecurity Machine learning Side channel attack Spectre Runtime Instructions RISC-V |
| Sumario: | Dataset containing a count of instructions executed by the proof-of-concept programs presented in the IEEE S&P 2023 paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" with side-channel attacks (spectre, spectre-v1, access-retired, zigzagger, interrupt-timing, timer-drift, page-walk, evict-reload, fence-flush, prime_probe, iflush-reload, flush-reload, flush-flush, tlb-evict, flush-fault) with a total of 20 programs; along with the data obtained for 20 benign programs/reference sets (as, b2sum, base32, base64, basicmath, bitcount, bzip2, cat, cksum, cmp, colrm, cut, dpkg, factor, ffmpeg, matrixmult, stream, stressC, stressM, gcc). All programs run on an emulated RISC-V architecture, specifically with QEMU 8.2.2 with RV64GCV architecture. |
|---|