Functional verification of a RISC-V vector accelerator
We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector accelerator, we built a verification infrastructure consisting of a UVM environment,...
| Autores: | , , , , , , , , , , , |
|---|---|
| Tipo de recurso: | artículo |
| Fecha de publicación: | 2023 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/382717 |
| Acceso en línea: | https://hdl.handle.net/2117/382717 https://dx.doi.org/10.1109/MDAT.2022.3226709 |
| Access Level: | acceso abierto |
| Palabra clave: | Microprocessors -- Verification European Processor Initiative (EPI) Verification RISC-V Vector accelerator UVM Coverage Random binary generation Microprocessadors -- Verificació Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector accelerator, we built a verification infrastructure consisting of a UVM environment, performing step by step co-simulation of all vector instructions, using the Spike instruction set simulator as a reference model. Furthermore, for validating this complex design connected to a scalar core using a custom interface, we provided automated constrained-random test generation, simulation and error reporting, and CI/CD infrastructure. We found 3005 errors during this process and reached 95.79% functional coverage. |
|---|