A hardware runtime for task-based programming models

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to se...

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Authors: Tan, Xubin, Bosch, Jaume, Álvarez, Carlos, Jiménez González, Daniel|||0000-0001-6064-7883, Ayguadé Parra, Eduard|||0000-0002-5146-103X, Valero Cortés, Mateo|||0000-0003-2917-2482
Format: article
Publication Date:2019
Country:España
Institution:Universitat Politècnica de Catalunya (UPC)
Repository:UPCommons. Portal del coneixement obert de la UPC
Language:English
OAI Identifier:oai:upcommons.upc.edu:2117/173031
Online Access:https://hdl.handle.net/2117/173031
https://dx.doi.org/10.1109/TPDS.2019.2907493
Access Level:Open access
Keyword:Field programmable gate arrays
Multiprocessors
Parallel processing (Electronic computers)
Fine-grained parallelism
Task-dependence analysis
Nested tasks
Heterogeneous task scheduling
Energy saving
FPGA
Task-based programming models
Matrius de portes programables per l'usuari
Multiprocessadors
Processament en paral·lel (Ordinadors)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
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Summary:© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

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