A hardware runtime for task-based programming models
© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to se...
| Autores: | , , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2019 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/173031 |
| Acceso en línea: | https://hdl.handle.net/2117/173031 https://dx.doi.org/10.1109/TPDS.2019.2907493 |
| Access Level: | acceso abierto |
| Palabra clave: | Field programmable gate arrays Multiprocessors Parallel processing (Electronic computers) Fine-grained parallelism Task-dependence analysis Nested tasks Heterogeneous task scheduling Energy saving FPGA Task-based programming models Matrius de portes programables per l'usuari Multiprocessadors Processament en paral·lel (Ordinadors) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
| Sumario: | © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
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