Hardware implementation of a FPGA-based universal link for LVDS communications
We present the first hardware implementation for a FPGA-based universal link for the transmission of different low-voltage differential signaling (LVDS) connections through a single LVDS connection between different devices. The main objective of this work is to reduce the number of wires in a netwo...
| Autores: | , , , |
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| Tipo de documento: | artigo |
| Data de publicação: | 2015 |
| País: | Perú |
| Recursos: | Universidad de Ingeniería y tecnología |
| Repositório: | UTEC-Institucional |
| Idioma: | inglês |
| OAI Identifier: | oai:repositorio.utec.edu.pe:20.500.12815/32 |
| Acesso em linha: | https://hdl.handle.net/20.500.12815/32 https://doi.org/10.1109/LASCAS.2015.7250480 |
| Access Level: | Acceso aberto |
| Palavra-chave: | Protocols Hardware Frequency division multiplexing, Optimization, Wires Field programmable gate arrays |
| Resumo: | We present the first hardware implementation for a FPGA-based universal link for the transmission of different low-voltage differential signaling (LVDS) connections through a single LVDS connection between different devices. The main objective of this work is to reduce the number of wires in a network, for example in some satellites, with several groups of devices, to a single LVDS connection. This paper proposes a new communication protocol for successfully coding and decoding the data sent through the single connection. We propose a solution for one of the difficulties of LVDS standard due to the amount of wires needed for a duplex connection, significantly reducing the amount of wires required for a large network. The proposed solution has been implemented in an Atlys board with a Spartan 6 FPGA showing promising results. |
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