Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

As microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltag...

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Detalles Bibliográficos
Autores: Rangel-Patiño, Francisco E., Rayas-Sánchez, José E., Hakim, Nagib
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2018
País:México
Institución:Instituto Tecnológico y de Estudios Superiores de Occidente
Repositorio:Repositorio Institucional del ITESO
Idioma:inglés
OAI Identifier:oai:rei.iteso.mx:11117/6010
Acceso en línea:http://hdl.handle.net/11117/6010
Access Level:acceso abierto
Palabra clave:Artificial Neural Networks (ANN)
Channel
Crosstalk
CTLE
DoE
Equalization
Ethernet
Eye Diagram
FIR
HSIO
ISI
Jitter
Kriging
Metamodels
Optimization
PCIe
Post-silicon Validation
Receiver
SATA
SFP
Signal Integrity
Space Mapping
Surrogates
System Margining
Transmitter
Tuning
USB
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spelling Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon ValidationRangel-Patiño, Francisco E.Rayas-Sánchez, José E.Hakim, NagibArtificial Neural Networks (ANN)ChannelCrosstalkCTLEDoEEqualizationEthernetEye DiagramFIRHSIOISIJitterKrigingMetamodelsOptimizationPCIePost-silicon ValidationReceiverSATASFPSignal IntegritySpace MappingSurrogatesSystem MarginingTransmitterTuningUSBAs microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltage, and temperature conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors. Many of them correspond to high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this work, direct and surrogate-based optimization methods, including space mapping, are proposed based on suitable objective functions to efficiently tune the transmitter and receiver equalizers. The proposed methodologies are evaluated by lab measurements on realistic industrial post-silicon validation platforms, confirming dramatic speed up in PHY tuning and substantial performance improvement.IEEE2019-08-30T19:01:23Z2019-08-30T19:01:23Z2018-10info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionapplication/pdfF. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim, “Transmitter and receiver equalizers optimization methodologies for high-speed links in industrial computer platforms post-silicon validation,” in Int. Test Conf. (ITC-2018), Phoenix, AZ, Oct. 2018, pp. 1-10. DOI: 10.1109/TEST.2018.86247941089-3539http://hdl.handle.net/11117/6010reponame:Repositorio Institucional del ITESOinstname:Instituto Tecnológico y de Estudios Superiores de Occidenteinstacron:ITESOengInternational Test Conference (ITC-2018);http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfinfo:eu-repo/semantics/openAccessoai:rei.iteso.mx:11117/60102024-10-04T18:55:57Z
dc.title.none.fl_str_mv Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
title Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
spellingShingle Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
Rangel-Patiño, Francisco E.
Artificial Neural Networks (ANN)
Channel
Crosstalk
CTLE
DoE
Equalization
Ethernet
Eye Diagram
FIR
HSIO
ISI
Jitter
Kriging
Metamodels
Optimization
PCIe
Post-silicon Validation
Receiver
SATA
SFP
Signal Integrity
Space Mapping
Surrogates
System Margining
Transmitter
Tuning
USB
title_short Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
title_full Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
title_fullStr Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
title_full_unstemmed Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
title_sort Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
dc.creator.none.fl_str_mv Rangel-Patiño, Francisco E.
Rayas-Sánchez, José E.
Hakim, Nagib
author Rangel-Patiño, Francisco E.
author_facet Rangel-Patiño, Francisco E.
Rayas-Sánchez, José E.
Hakim, Nagib
author_role author
author2 Rayas-Sánchez, José E.
Hakim, Nagib
author2_role author
author
dc.subject.none.fl_str_mv Artificial Neural Networks (ANN)
Channel
Crosstalk
CTLE
DoE
Equalization
Ethernet
Eye Diagram
FIR
HSIO
ISI
Jitter
Kriging
Metamodels
Optimization
PCIe
Post-silicon Validation
Receiver
SATA
SFP
Signal Integrity
Space Mapping
Surrogates
System Margining
Transmitter
Tuning
USB
topic Artificial Neural Networks (ANN)
Channel
Crosstalk
CTLE
DoE
Equalization
Ethernet
Eye Diagram
FIR
HSIO
ISI
Jitter
Kriging
Metamodels
Optimization
PCIe
Post-silicon Validation
Receiver
SATA
SFP
Signal Integrity
Space Mapping
Surrogates
System Margining
Transmitter
Tuning
USB
description As microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltage, and temperature conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors. Many of them correspond to high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this work, direct and surrogate-based optimization methods, including space mapping, are proposed based on suitable objective functions to efficiently tune the transmitter and receiver equalizers. The proposed methodologies are evaluated by lab measurements on realistic industrial post-silicon validation platforms, confirming dramatic speed up in PHY tuning and substantial performance improvement.
publishDate 2018
dc.date.none.fl_str_mv 2018-10
2019-08-30T19:01:23Z
2019-08-30T19:01:23Z
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv F. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim, “Transmitter and receiver equalizers optimization methodologies for high-speed links in industrial computer platforms post-silicon validation,” in Int. Test Conf. (ITC-2018), Phoenix, AZ, Oct. 2018, pp. 1-10. DOI: 10.1109/TEST.2018.8624794
1089-3539
http://hdl.handle.net/11117/6010
identifier_str_mv F. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim, “Transmitter and receiver equalizers optimization methodologies for high-speed links in industrial computer platforms post-silicon validation,” in Int. Test Conf. (ITC-2018), Phoenix, AZ, Oct. 2018, pp. 1-10. DOI: 10.1109/TEST.2018.8624794
1089-3539
url http://hdl.handle.net/11117/6010
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv International Test Conference (ITC-2018);
dc.rights.none.fl_str_mv http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf
info:eu-repo/semantics/openAccess
rights_invalid_str_mv http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv IEEE
publisher.none.fl_str_mv IEEE
dc.source.none.fl_str_mv reponame:Repositorio Institucional del ITESO
instname:Instituto Tecnológico y de Estudios Superiores de Occidente
instacron:ITESO
instname_str Instituto Tecnológico y de Estudios Superiores de Occidente
instacron_str ITESO
institution ITESO
reponame_str Repositorio Institucional del ITESO
collection Repositorio Institucional del ITESO
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1858177276695281664
score 15,811543

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