Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
As microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltag...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2018 |
| País: | México |
| Institución: | Instituto Tecnológico y de Estudios Superiores de Occidente |
| Repositorio: | Repositorio Institucional del ITESO |
| Idioma: | inglés |
| OAI Identifier: | oai:rei.iteso.mx:11117/6010 |
| Acceso en línea: | http://hdl.handle.net/11117/6010 |
| Access Level: | acceso abierto |
| Palabra clave: | Artificial Neural Networks (ANN) Channel Crosstalk CTLE DoE Equalization Ethernet Eye Diagram FIR HSIO ISI Jitter Kriging Metamodels Optimization PCIe Post-silicon Validation Receiver SATA SFP Signal Integrity Space Mapping Surrogates System Margining Transmitter Tuning USB |
| Sumario: | As microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltage, and temperature conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors. Many of them correspond to high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this work, direct and surrogate-based optimization methods, including space mapping, are proposed based on suitable objective functions to efficiently tune the transmitter and receiver equalizers. The proposed methodologies are evaluated by lab measurements on realistic industrial post-silicon validation platforms, confirming dramatic speed up in PHY tuning and substantial performance improvement. |
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