PVT compensated OTA design on SOI-CMOS nanometer technologies
In this study the design of a PVT compensated rail-to-rail input stage with constant transconductance and a high gain stage are presented, with the aim of providing a robust alternative to the problem of constant transconductance, reduced gain and at-band gain's variation of amplifiers in nanom...
| Autor: | |
|---|---|
| Tipo de documento: | dissertação |
| Estado: | Versión aceptada para publicación |
| Data de publicação: | 2012 |
| País: | México |
| Recursos: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositório: | Repositorio Institucional del INAOE |
| Idioma: | inglês |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/781 |
| Acesso em linha: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/781 |
| Access Level: | Acceso aberto |
| Palavra-chave: | info:eu-repo/classification/Circuitos integrados analógicos CMOS/CMOS analogue integrated circuits info:eu-repo/classification/Circuitos de procesamiento analógico/Analogue processing circuits info:eu-repo/classification/Amplificadores/Amplifiers info:eu-repo/classification/Amplificadores diferenciales/Differential amplifiers info:eu-repo/classification/Amplificadores operacionales/Operational amplifiers info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
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| dc.title.none.fl_str_mv |
PVT compensated OTA design on SOI-CMOS nanometer technologies |
| title |
PVT compensated OTA design on SOI-CMOS nanometer technologies |
| spellingShingle |
PVT compensated OTA design on SOI-CMOS nanometer technologies FRANCISCO JAVIER VILLOTA SALAZAR info:eu-repo/classification/Circuitos integrados analógicos CMOS/CMOS analogue integrated circuits info:eu-repo/classification/Circuitos de procesamiento analógico/Analogue processing circuits info:eu-repo/classification/Amplificadores/Amplifiers info:eu-repo/classification/Amplificadores diferenciales/Differential amplifiers info:eu-repo/classification/Amplificadores operacionales/Operational amplifiers info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/2203 |
| title_short |
PVT compensated OTA design on SOI-CMOS nanometer technologies |
| title_full |
PVT compensated OTA design on SOI-CMOS nanometer technologies |
| title_fullStr |
PVT compensated OTA design on SOI-CMOS nanometer technologies |
| title_full_unstemmed |
PVT compensated OTA design on SOI-CMOS nanometer technologies |
| title_sort |
PVT compensated OTA design on SOI-CMOS nanometer technologies |
| dc.creator.none.fl_str_mv |
FRANCISCO JAVIER VILLOTA SALAZAR |
| author |
FRANCISCO JAVIER VILLOTA SALAZAR |
| author_facet |
FRANCISCO JAVIER VILLOTA SALAZAR |
| author_role |
author |
| dc.contributor.none.fl_str_mv |
GUILLERMO ESPINOSA FLORES VERDAD |
| dc.subject.none.fl_str_mv |
info:eu-repo/classification/Circuitos integrados analógicos CMOS/CMOS analogue integrated circuits info:eu-repo/classification/Circuitos de procesamiento analógico/Analogue processing circuits info:eu-repo/classification/Amplificadores/Amplifiers info:eu-repo/classification/Amplificadores diferenciales/Differential amplifiers info:eu-repo/classification/Amplificadores operacionales/Operational amplifiers info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/2203 |
| topic |
info:eu-repo/classification/Circuitos integrados analógicos CMOS/CMOS analogue integrated circuits info:eu-repo/classification/Circuitos de procesamiento analógico/Analogue processing circuits info:eu-repo/classification/Amplificadores/Amplifiers info:eu-repo/classification/Amplificadores diferenciales/Differential amplifiers info:eu-repo/classification/Amplificadores operacionales/Operational amplifiers info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/2203 |
| description |
In this study the design of a PVT compensated rail-to-rail input stage with constant transconductance and a high gain stage are presented, with the aim of providing a robust alternative to the problem of constant transconductance, reduced gain and at-band gain's variation of amplifiers in nanometer technologies. Initially, an overview about the main concerns to downscaling in transistor sizing and some characteristics and details about SOI nanometer technology are given in order to identify the advantages and drawbacks with respect to CMOS technology. Subsequently, a solution to the sizing problem in current technology is adopted, which make the design of circuits possible. A rail-to-rail input stage with constant transconductance is designed, whose outstanding characteristics are the high robustness to PVT variations and the easy integration with other stages. These characteristics are obtained using the Feedback Differential Pair (FDP) circuit, improving the biasing, sub-threshold region for input differential pairs and an addition current circuit with opposite behavior in temperature with respect to the input signal section. For the gain stage design, first the problem of at-band gain's variation had to be solved. Then, some topologies to obtain high gain are reviewed, and at the same time some design considerations are reviewed and proposed in order to identify robust topologies. Applying these considerations and the transconductance addition technique, a two stage amplifier with two transconductance additions is proposed, which reaches a high gain value without using cascode structures or boosting techniques. Finally, the two designed circuits are integrated as an OTA circuit, which is fully characterized including PVT and Monte Carlo simulations in order to verify that all the design considerations were correct. |
| publishDate |
2012 |
| dc.date.none.fl_str_mv |
2012-08 |
| dc.type.none.fl_str_mv |
info:eu-repo/semantics/masterThesis info:eu-repo/semantics/acceptedVersion |
| format |
masterThesis |
| status_str |
acceptedVersion |
| dc.identifier.none.fl_str_mv |
http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/781 |
| url |
http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/781 |
| dc.language.none.fl_str_mv |
eng |
| language |
eng |
| dc.relation.none.fl_str_mv |
citation:Villota-Salazar F.J. |
| dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc-nd/4.0 |
| eu_rights_str_mv |
openAccess |
| rights_invalid_str_mv |
http://creativecommons.org/licenses/by-nc-nd/4.0 |
| dc.format.none.fl_str_mv |
application/pdf |
| dc.publisher.none.fl_str_mv |
Instituto Nacional de Astrofísica, Óptica y Electrónica |
| publisher.none.fl_str_mv |
Instituto Nacional de Astrofísica, Óptica y Electrónica |
| dc.source.none.fl_str_mv |
reponame:Repositorio Institucional del INAOE instname:Instituto Nacional de Astrofísica, Óptica y Electrónica instacron:INAOE |
| instname_str |
Instituto Nacional de Astrofísica, Óptica y Electrónica |
| instacron_str |
INAOE |
| institution |
INAOE |
| reponame_str |
Repositorio Institucional del INAOE |
| collection |
Repositorio Institucional del INAOE |
| repository.name.fl_str_mv |
|
| repository.mail.fl_str_mv |
|
| _version_ |
1858177117722771456 |
| spelling |
PVT compensated OTA design on SOI-CMOS nanometer technologiesFRANCISCO JAVIER VILLOTA SALAZARinfo:eu-repo/classification/Circuitos integrados analógicos CMOS/CMOS analogue integrated circuitsinfo:eu-repo/classification/Circuitos de procesamiento analógico/Analogue processing circuitsinfo:eu-repo/classification/Amplificadores/Amplifiersinfo:eu-repo/classification/Amplificadores diferenciales/Differential amplifiersinfo:eu-repo/classification/Amplificadores operacionales/Operational amplifiersinfo:eu-repo/classification/cti/1info:eu-repo/classification/cti/22info:eu-repo/classification/cti/2203info:eu-repo/classification/cti/2203In this study the design of a PVT compensated rail-to-rail input stage with constant transconductance and a high gain stage are presented, with the aim of providing a robust alternative to the problem of constant transconductance, reduced gain and at-band gain's variation of amplifiers in nanometer technologies. Initially, an overview about the main concerns to downscaling in transistor sizing and some characteristics and details about SOI nanometer technology are given in order to identify the advantages and drawbacks with respect to CMOS technology. Subsequently, a solution to the sizing problem in current technology is adopted, which make the design of circuits possible. A rail-to-rail input stage with constant transconductance is designed, whose outstanding characteristics are the high robustness to PVT variations and the easy integration with other stages. These characteristics are obtained using the Feedback Differential Pair (FDP) circuit, improving the biasing, sub-threshold region for input differential pairs and an addition current circuit with opposite behavior in temperature with respect to the input signal section. For the gain stage design, first the problem of at-band gain's variation had to be solved. Then, some topologies to obtain high gain are reviewed, and at the same time some design considerations are reviewed and proposed in order to identify robust topologies. Applying these considerations and the transconductance addition technique, a two stage amplifier with two transconductance additions is proposed, which reaches a high gain value without using cascode structures or boosting techniques. Finally, the two designed circuits are integrated as an OTA circuit, which is fully characterized including PVT and Monte Carlo simulations in order to verify that all the design considerations were correct.En este trabajo se presenta el diseño de una etapa de entrada de riel a riel con transconductancia constante y una etapa de alta ganancia, con el objetivo de proporcionar una alternativa robusta a los problemas de obtener transconductancia constante, baja ganancia y variación de esta en bajas frecuencias para los amplificadores en tecnologías nanométricas. Inicialmente se presenta una breve introducción acerca de los principales inconvenientes de la reducción de tamaño en las dimensiones del transistor, luego se explican algunas características y detalles acerca de la tecnología SOI de escala nanométrica, esto con el fin de identificar las ventajas y desventajas con respecto a la tecnología CMOS. Posteriormente, se adopta una solución al problema de dimensionamiento en la tecnología empleada, lo cual permite el diseño de los circuitos en la tecnología anteriormente mencionada. Se diseña una etapa de entrada de riel a riel con transconductancia constante, cuyas características más sobresalientes son la robustez a variaciones PVT y su fácil acoplamiento con otras etapas. Estas características se obtienen usando el circuito de par diferencial realimentado (FDP), mejorando la polarización, la región de sub-umbral para los pares diferenciales de entrada y un circuito de suma de corrientes con comportamiento opuesto en temperatura con respecto a la sección de entrada de señal. Para el diseño de la etapa de ganancia, primero se resuelve el problema de variación de ganancia en baja frecuencia. Entonces se revisan algunas topologías para obtener alta ganancia, al mismo tiempo se proponen y revisan consideraciones de diseño con el fin de identificar las topologías robustas. Aplicando estas consideraciones y la técnica de suma de transconductancias, se propone un amplificador de dos etapas con dos sumas de transconductancia, el cual alcanza valores altos de ganancia sin el uso de estructuras tipo cascodo o técnicas de boosting. Finalmente, los dos circuitos diseñados son acoplados como un OTA, el cual es completamente caracterizado incluyendo simulaciones PVT y Montecarlo con el _n de verificar que todas las consideraciones de diseño fueron correctas.Instituto Nacional de Astrofísica, Óptica y ElectrónicaGUILLERMO ESPINOSA FLORES VERDAD2012-08info:eu-repo/semantics/masterThesisinfo:eu-repo/semantics/acceptedVersionapplication/pdfhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/781reponame:Repositorio Institucional del INAOEinstname:Instituto Nacional de Astrofísica, Óptica y Electrónicainstacron:INAOEengcitation:Villota-Salazar F.J.info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-nd/4.0oai:inaoe.repositorioinstitucional.mx:1009/7812024-08-28T03:22:48Z |
| score |
14,964248 |