New High-Performance Full Adders Using an Alternative Logic Structure
This paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logic structure, and the logic styles DPL and SR-CPL. The adders were designed using electrical parameters of a 0.35µm Complementary Metal-Oxide-Semiconductor (CMOS) process, and were compared with various a...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2011 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Redalyc-INAOE |
| OAI Identifier: | oai:redalyc.org:61520765002 |
| Acceso en línea: | https://www.redalyc.org/articulo.oa?id=61520765002 |
| Access Level: | acceso abierto |
| Palabra clave: | Computación Low Full adder power Pipeline |
| Sumario: | This paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logic structure, and the logic styles DPL and SR-CPL. The adders were designed using electrical parameters of a 0.35µm Complementary Metal-Oxide-Semiconductor (CMOS) process, and were compared with various adders published previously, with regards of power-delay product. To validate the performance simulation results of one of the proposed adders, an 8-bits pipelined multiplier was fabricated using a 0.35µm CMOS technology, and it showed to provide superior performance. |
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