New High-Performance Full Adders Using an Alternative Logic Structure
Abstract. This paper presents two new high-speed lowpower 1-bit full-adder cells using an alternative logic structure, and the logic styles DPL and SR-CPL. The adders were designed using electrical parameters of a 0.35μm Complementary Metal-Oxide-Semiconductor (CMOS) process, and were compared with...
| Autores: | , |
|---|---|
| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2011 |
| País: | México |
| Institución: | Instituto Politécnico Nacional |
| Repositorio: | Repositorio Digital del IPN |
| OAI Identifier: | oai:www.repositoriodigital.ipn.mx:123456789/15012 |
| Acceso en línea: | http://www.repositoriodigital.ipn.mx/handle/123456789/15012 |
| Access Level: | acceso abierto |
| Palabra clave: | Keywords. Full-adder, Low-power, Multiplier, Pipeline. |
| Sumario: | Abstract. This paper presents two new high-speed lowpower 1-bit full-adder cells using an alternative logic structure, and the logic styles DPL and SR-CPL. The adders were designed using electrical parameters of a 0.35μm Complementary Metal-Oxide-Semiconductor (CMOS) process, and were compared with various adders published previously, with regards of power-delay product. To validate the performance simulation results of one of the proposed adders, an 8-bits pipelined multiplier was fabricated using a 0.35μm CMOS technology, and it showed to provide superior performance. |
|---|