Estudio y desarrollo de celdas solares basadas en estructuras de silicio cristalino / silicio amorfo dopado.
In this work, a process of manufacturing of HIT solar cells were developed, known as heterojunction cells between crystalline silicon N type substrate with a P-doped amorphous silicon as emitter and a thin Passivation layer of intrinsic amorphous silicon. They also have a n-doped amorphous silicon l...
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| Formato: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2018 |
| País: | México |
| Recursos: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | español |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/1467 |
| Acesso em linha: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1467 |
| Access Level: | acceso abierto |
| Palavra-chave: | info:eu-repo/classification/Inspec/Cells HIT info:eu-repo/classification/Inspec/Crystalline silicon / Amorphous silicon info:eu-repo/classification/Inspec/Solar cell info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
| Resumo: | In this work, a process of manufacturing of HIT solar cells were developed, known as heterojunction cells between crystalline silicon N type substrate with a P-doped amorphous silicon as emitter and a thin Passivation layer of intrinsic amorphous silicon. They also have a n-doped amorphous silicon layer as back surface field. The junction between crystalline silicon and doped amorphous silicon presents recombination centers, which impact in the decrease of the short circuit current (Isc) and open circuit voltage (Voc). To improve this junction, a thin layer of intrinsic amorphous silicon was deposited (i a-Si:H) with a thickness of 8 ± 2nm. This structure gets an Isc of 43 ± 2mA and a Voc of 0.44 ± 0.02 V. Increasing the thickness of this intrinsic film increases the Voc but decreases the Isc. Other methods have been analyzed and studied to improve this Voc without diminishing Isc. The crystalline silicon substrate texturing improves the absorption of solar energy, which increases the Isc, but creates additional crystalline defects in the surface of the pyramids, then a wet passivation method was used, which consists on oxidation and etching cycles until eliminating these defects in the surface of the pyramids, keeping the Isc in 43 ± 2mA and improving the Voc at 0.5V. Finally, for a Voc improvement, without reducing the Isc, the substrate was texturized leaving the aluminum contacts area without texturing, obtaining a Voc of 0.54 V and the Isc at 43 ± 2mA. To protect the amorphous films from environment, for collecting the generated hole-electron pairs, to improve the filling factor (F.F) and as anti-reflecting film, a transparent conductive oxide (TCO) film was deposited (Indium Tin Oxide, ITO) on both sides and finally aluminum contacts were evaporated. The results obtained in this work, compared with previous works made at INAOE, in the manufacture of heterojunction cells was possible to increase the efficiency from 5.8% to 10.5%. In addition, a superior short circuit current of 45mA was obtained even more than the records reported by PANASONIC and KANEKA. |
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