Karatsuba-Ofman Multiplier with Integrated Modular Reduction for (2m )
In this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the origin...
| Autores: | , , , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2013 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | inglés |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/2396 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2396 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Data security/Data security info:eu-repo/classification/Cryptography/Cryptography info:eu-repo/classification/Public key/Public key info:eu-repo/classification/Algorithm design and analysis/Algorithm design and analysis info:eu-repo/classification/Field programmable gate arrays/Field programmable gate arrays info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/12 info:eu-repo/classification/cti/1203 |
| Sumario: | In this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel linear feedback registers. The new algorithm is described in detail and results from a hardware implementation on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6 device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed multiplier uses 36% less area resources and improves the maximum delay in 10%. |
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