Arquitectura hardware para la detección de puntos de interés del SIFT
The use of local features in images has become very popular thanks to its promising results. These have shown significant benefits in a variety of applications such as object recognition, image retrieval, robot navigation, panorama stitching, and others. Several algorithms have been developed in thi...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2010 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | español |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/495 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/495 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Field programmable gate arrays/Field programmable gate arrays info:eu-repo/classification/Características locales/Local features info:eu-repo/classification/Escala invariante/Scale invariant info:eu-repo/classification/Features transform/Features transform info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/12 info:eu-repo/classification/cti/1203 |
| Sumario: | The use of local features in images has become very popular thanks to its promising results. These have shown significant benefits in a variety of applications such as object recognition, image retrieval, robot navigation, panorama stitching, and others. Several algorithms have been developed in this area. One of the most popular and widely used is the SIFT method. This algorithm finds local structures that are present in different views of the image. It also allows a description of these structures invariant to image transformations such as translation, rotation, scale and affine transformations. However, its main disadvantage is its high computational cost. This arises the need to seek alternatives to its acceleration. To that end, this paper proposes a design and implementation of an efficient hardware architecture based on FPGAs (Field Programmable Gate Array) for the candidate keypoints detection stage of the SIFT algorithm. In order to take full advantage of the parallelism in the candidate keypoints detection stage and to minimize the silicon area occupied by its implementation in hardware, part of the algorithm was reformulated. The main characteristics of this reformulation are the exploitation of data parallelism, the exploitation of the separability property of the Gaussian kernel and the octaves processing interleaving. The main contribution of the proposed pipelined architecture and the main difference with the rest of the architectures reported in the literature, is that while increasing the number of octaves to be processed, the amount of occupied area of the device remains almost constant, only increased in the number of blocks of memory needed to store the new octaves and in the logic needed to control the interleaving of more octaves. The tests and experiments conducted to the architecture evidenced the contribution mentioned above, as well as accuracy, repeatability and distinctiveness of the extracted features. Tests are also related to device area occupation, timing constraints, among others. The architecture presented in this work is able to detect candidate keypoints in an image of 320 × 240 in 1.1 milliseconds, which represents a speedup of 250x with respect to a software implementation. |
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