High performance voltage follower with very low output resistance for WTA applications
A modification of the conventional Flipped Voltage Follower (FVF) to enhance its output resistance is presented. It consists of replacing the conventional cascoding transistor of the basic cell by a regulated cascode scheme. This decreases the output resistance by a factor gmro approximately, the ga...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2014 |
| País: | México |
| Institución: | Instituto Tecnológico y de Estudios Superiores de Occidente |
| Repositorio: | Repositorio Institucional del ITESO |
| Idioma: | inglés |
| OAI Identifier: | oai:rei.iteso.mx:11117/2918 |
| Acceso en línea: | http://hdl.handle.net/11117/2918 |
| Access Level: | acceso abierto |
| Palabra clave: | Winner-Take-All (WTA) Analog Circuits Voltage Follower Analog CMOS Integrated Circuits Integrated Circuits |
| Sumario: | A modification of the conventional Flipped Voltage Follower (FVF) to enhance its output resistance is presented. It consists of replacing the conventional cascoding transistor of the basic cell by a regulated cascode scheme. This decreases the output resistance by a factor gmro approximately, the gain of a transistor as an amplifying stage. This is achieved with only two additional transistors and a biasing current IB, offering a significant advantage with respect to other previously reported architectures that require considerably increased power consumption and number of devices. Simulation results in 0.5 µm technology show an enhancement factor of 16, approximately, with respect to the conventional FVF, resulting in an output resistance of 3.1 Ω. Additionally, the proposed follower was implemented in a winner-take-all circuit to prove its functionality; simulation and experimental results confirm the proposed operation. |
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