A Low-Complexity current-mode WTA circuit based on CMOS Quasi-FG Inverters
In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with logical outputs is presented. The proposed approach employs a Quasi-FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double...
| Autores: | , , , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2011 |
| País: | México |
| Institución: | Universidad Autónoma del Estado de México |
| Repositorio: | Redalyc-UAEMEX |
| OAI Identifier: | oai:redalyc.org:61520765004 |
| Acceso en línea: | https://www.redalyc.org/articulo.oa?id=61520765004 |
| Access Level: | acceso abierto |
| Palabra clave: | Computación all take Winner neural networks analog circuits |
| Sumario: | In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with logical outputs is presented. The proposed approach employs a Quasi-FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double-poly, three metal layers, 0.5µm CMOS technology. The circuit exhibits a good accuracy-speed tradeoff when compared to other reported WTA architectures. |
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