A fault-tolerant last level cache for CMPs operating at ultra-low voltage

Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block disabling is a micro-architectural technique that...

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Autores: Ferrerón, A., Alastruey-Benedé, J., Suárez Gracia, D., Monreal Arnal, T., Ibáñez Marín, P., Viñals Yúfera, V.
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2019
País:España
Institución:Universidad de Zaragoza
Repositorio:Zaguán. Repositorio Digital de la Universidad de Zaragoza
OAI Identifier:oai:zaguan.unizar.es:84684
Acceso en línea:http://zaguan.unizar.es/record/84684
Access Level:acceso abierto
id ES_fe4e8c209dab693d5b29913d65ce84d6
oai_identifier_str oai:zaguan.unizar.es:84684
network_acronym_str ES
network_name_str España
repository_id_str
spelling A fault-tolerant last level cache for CMPs operating at ultra-low voltageFerrerón, A.Alastruey-Benedé, J.Suárez Gracia, D.Monreal Arnal, T.Ibáñez Marín, P.Viñals Yúfera, V.Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block disabling is a micro-architectural technique that allows low-voltage operation by deactivating faulty cache entries, at the expense of reducing the effective cache capacity. In the case of the last-level cache, this capacity reduction leads to an increase in off-chip memory accesses, diminishing the overall energy benefit of reducing the voltage supply. In this work, we exploit the reuse locality and the intrinsic redundancy of multi-level inclusive hierarchies to enhance the performance of block disabling with negligible cost. The proposed fault-aware last-level cache management policy maps critical blocks, those not present in private caches and with a higher probability of being reused, to active cache entries. Our evaluation shows that this fault-aware management results in up to 37.3% and 54.2% fewer misses per kilo instruction (MPKI) than block disabling for multiprogrammed and parallel workloads, respectively. This translates to performance enhancements of up to 13% and 34.6% for multiprogrammed and parallel workloads, respectively.2019info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfhttp://zaguan.unizar.es/record/84684reponame:Zaguán. Repositorio Digital de la Universidad de Zaragozainstname:Universidad de ZaragozaInglésinfo:eu-repo/grantAgreement/ES/DGA/T58-17Rinfo:eu-repo/grantAgreement/ES/MINECO/TIN2015-65316-Pinfo:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-Rinfo:eu-repo/semantics/openAccessoai:zaguan.unizar.es:846842026-05-29T13:59:51Z
dc.title.none.fl_str_mv A fault-tolerant last level cache for CMPs operating at ultra-low voltage
title A fault-tolerant last level cache for CMPs operating at ultra-low voltage
spellingShingle A fault-tolerant last level cache for CMPs operating at ultra-low voltage
Ferrerón, A.
title_short A fault-tolerant last level cache for CMPs operating at ultra-low voltage
title_full A fault-tolerant last level cache for CMPs operating at ultra-low voltage
title_fullStr A fault-tolerant last level cache for CMPs operating at ultra-low voltage
title_full_unstemmed A fault-tolerant last level cache for CMPs operating at ultra-low voltage
title_sort A fault-tolerant last level cache for CMPs operating at ultra-low voltage
dc.creator.none.fl_str_mv Ferrerón, A.
Alastruey-Benedé, J.
Suárez Gracia, D.
Monreal Arnal, T.
Ibáñez Marín, P.
Viñals Yúfera, V.
author Ferrerón, A.
author_facet Ferrerón, A.
Alastruey-Benedé, J.
Suárez Gracia, D.
Monreal Arnal, T.
Ibáñez Marín, P.
Viñals Yúfera, V.
author_role author
author2 Alastruey-Benedé, J.
Suárez Gracia, D.
Monreal Arnal, T.
Ibáñez Marín, P.
Viñals Yúfera, V.
author2_role author
author
author
author
author
description Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block disabling is a micro-architectural technique that allows low-voltage operation by deactivating faulty cache entries, at the expense of reducing the effective cache capacity. In the case of the last-level cache, this capacity reduction leads to an increase in off-chip memory accesses, diminishing the overall energy benefit of reducing the voltage supply. In this work, we exploit the reuse locality and the intrinsic redundancy of multi-level inclusive hierarchies to enhance the performance of block disabling with negligible cost. The proposed fault-aware last-level cache management policy maps critical blocks, those not present in private caches and with a higher probability of being reused, to active cache entries. Our evaluation shows that this fault-aware management results in up to 37.3% and 54.2% fewer misses per kilo instruction (MPKI) than block disabling for multiprogrammed and parallel workloads, respectively. This translates to performance enhancements of up to 13% and 34.6% for multiprogrammed and parallel workloads, respectively.
publishDate 2019
dc.date.none.fl_str_mv 2019
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv http://zaguan.unizar.es/record/84684
url http://zaguan.unizar.es/record/84684
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv info:eu-repo/grantAgreement/ES/DGA/T58-17R
info:eu-repo/grantAgreement/ES/MINECO/TIN2015-65316-P
info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv
publisher.none.fl_str_mv
dc.source.none.fl_str_mv reponame:Zaguán. Repositorio Digital de la Universidad de Zaragoza
instname:Universidad de Zaragoza
instname_str Universidad de Zaragoza
reponame_str Zaguán. Repositorio Digital de la Universidad de Zaragoza
collection Zaguán. Repositorio Digital de la Universidad de Zaragoza
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869425673294053376
score 15,301603

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