Accelerating the evolution of a systolic array-based evolvable hardware system

Detalles Bibliográficos
Autores: Mora de Sambricio, Javier, Torre Arnanz, Eduardo de la|||0000-0001-5697-0573
Tipo de recurso: artículo
Fecha de publicación:2018
País:España
Institución:Universidad Politécnica de Madrid
Repositorio:Archivo Digital UPM
OAI Identifier:oai:oa.upm.es:54982
Acceso en línea:https://oa.upm.es/54982/
Access Level:acceso abierto
Palabra clave:FPGA
Evolvable hardware
Dynamic partial reconfiguration
Evolutionary algorithm
Systolic array
LUT
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spelling Accelerating the evolution of a systolic array-based evolvable hardware systemMora de Sambricio, JavierTorre Arnanz, Eduardo de la|||0000-0001-5697-0573FPGAEvolvable hardwareDynamic partial reconfigurationEvolutionary algorithmSystolic arrayLUT20182018-02-01journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articlehttps://oa.upm.es/54982/reponame:Archivo Digital UPMinstname:Universidad Politécnica de MadridInglésenopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:oa.upm.es:549822026-06-21T12:45:07Z
dc.title.none.fl_str_mv Accelerating the evolution of a systolic array-based evolvable hardware system
title Accelerating the evolution of a systolic array-based evolvable hardware system
spellingShingle Accelerating the evolution of a systolic array-based evolvable hardware system
Mora de Sambricio, Javier
FPGA
Evolvable hardware
Dynamic partial reconfiguration
Evolutionary algorithm
Systolic array
LUT
title_short Accelerating the evolution of a systolic array-based evolvable hardware system
title_full Accelerating the evolution of a systolic array-based evolvable hardware system
title_fullStr Accelerating the evolution of a systolic array-based evolvable hardware system
title_full_unstemmed Accelerating the evolution of a systolic array-based evolvable hardware system
title_sort Accelerating the evolution of a systolic array-based evolvable hardware system
dc.creator.none.fl_str_mv Mora de Sambricio, Javier
Torre Arnanz, Eduardo de la|||0000-0001-5697-0573
author Mora de Sambricio, Javier
author_facet Mora de Sambricio, Javier
Torre Arnanz, Eduardo de la|||0000-0001-5697-0573
author_role author
author2 Torre Arnanz, Eduardo de la|||0000-0001-5697-0573
author2_role author
dc.subject.none.fl_str_mv FPGA
Evolvable hardware
Dynamic partial reconfiguration
Evolutionary algorithm
Systolic array
LUT
topic FPGA
Evolvable hardware
Dynamic partial reconfiguration
Evolutionary algorithm
Systolic array
LUT
publishDate 2018
dc.date.none.fl_str_mv 2018
2018-02-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://oa.upm.es/54982/
url https://oa.upm.es/54982/
dc.language.none.fl_str_mv Inglés
en
language_invalid_str_mv Inglés
en
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv reponame:Archivo Digital UPM
instname:Universidad Politécnica de Madrid
instname_str Universidad Politécnica de Madrid
reponame_str Archivo Digital UPM
collection Archivo Digital UPM
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300719

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