A large-scale spiking neural networks emulation architecture

The purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a large-scale SNN emulator. It preserves the basic hardware structure of SNAVA, m...

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Detalles Bibliográficos
Autor: Pirrone, Vito
Tipo de recurso: tesis de maestría
Fecha de publicación:2014
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2099.1/22996
Acceso en línea:https://hdl.handle.net/2099.1/22996
Access Level:acceso abierto
Palabra clave:Neural networks (Computer science)
Spiking Neural Networks
SNN hardware emulator
hardware architecture
FPGA
Xarxes neuronals (Informàtica)
Àrees temàtiques de la UPC::Enginyeria de la telecomunicació
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oai_identifier_str oai:upcommons.upc.edu:2099.1/22996
network_acronym_str ES
network_name_str España
repository_id_str
spelling A large-scale spiking neural networks emulation architecturePirrone, VitoNeural networks (Computer science)Spiking Neural NetworksSNN hardware emulatorhardware architectureFPGAXarxes neuronals (Informàtica)Àrees temàtiques de la UPC::Enginyeria de la telecomunicacióThe purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a large-scale SNN emulator. It preserves the basic hardware structure of SNAVA, making however several changes to optimize the performance. In particular, SNAVA+ project focuses on the aim to exploit more efficiently the availables resources, to reduce both the area and power consumption of the FPGA. A better use of the resources, in fact, is the main key to increase the potentiality of the SNN emulator, i.e. to increase the number of neurons and synapses simulated.Universitat Politècnica de CatalunyaMadrenas Boadas, JordiSánchez Rivera, Giovanny20142014-09-0920142014-10-13master thesishttp://purl.org/coar/resource_type/c_bdccNAhttp://purl.org/coar/version/c_be7fb7dd8ff6fe43info:eu-repo/semantics/masterThesisapplication/pdfhttps://hdl.handle.net/2099.1/22996reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2http://creativecommons.org/licenses/by-nc-nd/3.0/es/info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2099.1/229962026-05-27T15:37:01Z
dc.title.none.fl_str_mv A large-scale spiking neural networks emulation architecture
title A large-scale spiking neural networks emulation architecture
spellingShingle A large-scale spiking neural networks emulation architecture
Pirrone, Vito
Neural networks (Computer science)
Spiking Neural Networks
SNN hardware emulator
hardware architecture
FPGA
Xarxes neuronals (Informàtica)
Àrees temàtiques de la UPC::Enginyeria de la telecomunicació
title_short A large-scale spiking neural networks emulation architecture
title_full A large-scale spiking neural networks emulation architecture
title_fullStr A large-scale spiking neural networks emulation architecture
title_full_unstemmed A large-scale spiking neural networks emulation architecture
title_sort A large-scale spiking neural networks emulation architecture
dc.creator.none.fl_str_mv Pirrone, Vito
author Pirrone, Vito
author_facet Pirrone, Vito
author_role author
dc.contributor.none.fl_str_mv Madrenas Boadas, Jordi
Sánchez Rivera, Giovanny
dc.subject.none.fl_str_mv Neural networks (Computer science)
Spiking Neural Networks
SNN hardware emulator
hardware architecture
FPGA
Xarxes neuronals (Informàtica)
Àrees temàtiques de la UPC::Enginyeria de la telecomunicació
topic Neural networks (Computer science)
Spiking Neural Networks
SNN hardware emulator
hardware architecture
FPGA
Xarxes neuronals (Informàtica)
Àrees temàtiques de la UPC::Enginyeria de la telecomunicació
description The purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a large-scale SNN emulator. It preserves the basic hardware structure of SNAVA, making however several changes to optimize the performance. In particular, SNAVA+ project focuses on the aim to exploit more efficiently the availables resources, to reduce both the area and power consumption of the FPGA. A better use of the resources, in fact, is the main key to increase the potentiality of the SNN emulator, i.e. to increase the number of neurons and synapses simulated.
publishDate 2014
dc.date.none.fl_str_mv 2014
2014-09-09
2014
2014-10-13
dc.type.none.fl_str_mv master thesis
http://purl.org/coar/resource_type/c_bdcc
NA
http://purl.org/coar/version/c_be7fb7dd8ff6fe43
dc.type.openaire.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2099.1/22996
url https://hdl.handle.net/2099.1/22996
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2

http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2

http://creativecommons.org/licenses/by-nc-nd/3.0/es/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869424668091351040
score 15,301603

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