A large-scale spiking neural networks emulation architecture
The purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a large-scale SNN emulator. It preserves the basic hardware structure of SNAVA, m...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2014 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2099.1/22996 |
| Acceso en línea: | https://hdl.handle.net/2099.1/22996 |
| Access Level: | acceso abierto |
| Palabra clave: | Neural networks (Computer science) Spiking Neural Networks SNN hardware emulator hardware architecture FPGA Xarxes neuronals (Informàtica) Àrees temàtiques de la UPC::Enginyeria de la telecomunicació |
| Sumario: | The purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a large-scale SNN emulator. It preserves the basic hardware structure of SNAVA, making however several changes to optimize the performance. In particular, SNAVA+ project focuses on the aim to exploit more efficiently the availables resources, to reduce both the area and power consumption of the FPGA. A better use of the resources, in fact, is the main key to increase the potentiality of the SNN emulator, i.e. to increase the number of neurons and synapses simulated. |
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