Fuzzy logic-based embedded system for video de-interlacing

Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-in...

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Detalles Bibliográficos
Autores: Brox, Piedad, Baturone, Iluminada, Sánchez-Solano, Santiago
Tipo de recurso: artículo
Fecha de publicación:2014
País:España
Institución:Consejo Superior de Investigaciones Científicas (CSIC)
Repositorio:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:digital.csic.es:10261/92707
Acceso en línea:http://hdl.handle.net/10261/92707
Access Level:acceso abierto
Palabra clave:IP core
Video de-interlacing
Fuzzy system
Embedded system
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spelling Fuzzy logic-based embedded system for video de-interlacingBrox, PiedadBaturone, IluminadaSánchez-Solano, SantiagoIP coreVideo de-interlacingFuzzy systemEmbedded systemVideo de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time. © 2013 Elsevier B.V. All rights reserved.This work was partially supported by MOBY-DIC project FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from EuropeanCommunity, TEC2011-24319 project from the Spanish Govern-ment, and P08-TIC-03674 project from the Andalusian Regional Government (with support from the PO FEDER). P. Brox is supportedunder the post-doctoral program called ‘Juan de la Cierva’ from theSpanish Ministry of Science and Innovation.Peer ReviewedElsevier2014201420142014info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_6501http://hdl.handle.net/10261/92707reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)Inglés#PLACEHOLDER_PARENT_METADATA_VALUE#info:eu-repo/grantAgreement/EC/FP7/248858info:eu-repo/semantics/openAccessoai:digital.csic.es:10261/927072026-05-22T06:33:51Z
dc.title.none.fl_str_mv Fuzzy logic-based embedded system for video de-interlacing
title Fuzzy logic-based embedded system for video de-interlacing
spellingShingle Fuzzy logic-based embedded system for video de-interlacing
Brox, Piedad
IP core
Video de-interlacing
Fuzzy system
Embedded system
title_short Fuzzy logic-based embedded system for video de-interlacing
title_full Fuzzy logic-based embedded system for video de-interlacing
title_fullStr Fuzzy logic-based embedded system for video de-interlacing
title_full_unstemmed Fuzzy logic-based embedded system for video de-interlacing
title_sort Fuzzy logic-based embedded system for video de-interlacing
dc.creator.none.fl_str_mv Brox, Piedad
Baturone, Iluminada
Sánchez-Solano, Santiago
author Brox, Piedad
author_facet Brox, Piedad
Baturone, Iluminada
Sánchez-Solano, Santiago
author_role author
author2 Baturone, Iluminada
Sánchez-Solano, Santiago
author2_role author
author
dc.subject.none.fl_str_mv IP core
Video de-interlacing
Fuzzy system
Embedded system
topic IP core
Video de-interlacing
Fuzzy system
Embedded system
description Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time. © 2013 Elsevier B.V. All rights reserved.
publishDate 2014
dc.date.none.fl_str_mv 2014
2014
2014
2014
dc.type.none.fl_str_mv info:eu-repo/semantics/article
http://purl.org/coar/resource_type/c_6501
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/10261/92707
url http://hdl.handle.net/10261/92707
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv #PLACEHOLDER_PARENT_METADATA_VALUE#
info:eu-repo/grantAgreement/EC/FP7/248858
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.publisher.none.fl_str_mv Elsevier
publisher.none.fl_str_mv Elsevier
dc.source.none.fl_str_mv reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC
instname:Consejo Superior de Investigaciones Científicas (CSIC)
instname_str Consejo Superior de Investigaciones Científicas (CSIC)
reponame_str DIGITAL.CSIC. Repositorio Institucional del CSIC
collection DIGITAL.CSIC. Repositorio Institucional del CSIC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.812429

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