Fuzzy logic-based embedded system for video de-interlacing
Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-in...
| Autores: | , , |
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| Formato: | artículo |
| Fecha de publicación: | 2014 |
| País: | España |
| Recursos: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositorio: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/92707 |
| Acesso em linha: | http://hdl.handle.net/10261/92707 |
| Access Level: | acceso abierto |
| Palavra-chave: | IP core Video de-interlacing Fuzzy system Embedded system |
| Resumo: | Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time. © 2013 Elsevier B.V. All rights reserved. |
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