A multicore emulator with a profiling infrastructure for transactional memory on FPGA

This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory multicore emulator with Hybrid Transactional Memory support, based on the P...

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Detalles Bibliográficos
Autor: Sönmez, Nehir
Tipo de recurso: tesis doctoral
Fecha de publicación:2012
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/104207
Acceso en línea:https://hdl.handle.net/2117/104207
https://dx.doi.org/10.5821/dissertation-2117-104207
Access Level:acceso abierto
Palabra clave:Simulació per ordinador
Gestió de memòria (Informàtica)
Àrees temàtiques de la UPC::Informàtica
id ES_efcc3cd4fcebab3c7e2ef0da86a59831
oai_identifier_str oai:upcommons.upc.edu:2117/104207
network_acronym_str ES
network_name_str España
repository_id_str
spelling A multicore emulator with a profiling infrastructure for transactional memory on FPGASönmez, NehirSimulació per ordinadorGestió de memòria (Informàtica)Àrees temàtiques de la UPC::InformàticaThis thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory multicore emulator with Hybrid Transactional Memory support, based on the Plasma open source soft processor core. We present the design and implementation of the TMbox system, which features an emulation system of up to 16 soft processor cores interconnected with a bi-directional ring bus, running at 50 MHz on a Virtex5-155t FPGA. Additionally, we build the first comprehensive infrastructure to profile Hybrid TM systems, an extensive visualization environment that enables examining complete transactional executions in detail. TMbox is a completely modifiable architecture implementing a multicore prototype with support for STM, HTM and Hybrid TM. It was written in various common design languages, and enables modifying the complete stack, down from the ISA, through the software toolchain, up to the well-optimized parallel code. With such an infrastructure, fast execution and quick performance evaluation can be made possible for studies in computer architecture.En esta tesis se propone juntar dos temas recientes a través de la creación de un sistema de memoria transaccional en un circuito programable (un FPGA). Para ello, ha sido diseñado un emulador de multinúcleo, con soporte para memoria transaccional híbrida y núcleos MIPS basados en el procesador de código libre Plasma. Presentamos el diseño y la implementación del sistema TMbox, que implementa un sistema de emulación de hasta 16 núcleos MIPS interconectados con un bus en anillo bidireccional, funcionando a 50 MHz en un FPGA Virtex5-155t. Adicionalmente, hemos construido la primera infraestructura para perfilado y visualización de memoria transaccional híbrida, que permite ver con un alto detalle ejecuciones transaccionales completas. TMbox es una arquitectura completamente modificable, e implementa un prototipo de un multinúcleo con memoria transaccional en software, hardware e híbrido. Está compuesto de varios lenguajes de diseño muy comunes, y habilita modificar el stack completo, desde la ISA, pasando por el toolchain de software, hasta el código paralelo altamente optimizado. Con una infraestructura como TMbox, es posible la ejecución veloz y la evaluación rápida del rendimiento en investigaciones de arquitectura de computadores.Universitat Politècnica de CatalunyaÜnsal, OsmanCristal Kestelman, Adrián20122012-09-1920172017-05-04doctoral thesishttp://purl.org/coar/resource_type/c_db06VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/doctoralThesisapplication/pdfhttps://hdl.handle.net/2117/104207https://dx.doi.org/10.5821/dissertation-2117-104207reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2http://creativecommons.org/licenses/by-nc-sa/4.0/info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/1042072026-05-27T15:37:01Z
dc.title.none.fl_str_mv A multicore emulator with a profiling infrastructure for transactional memory on FPGA
title A multicore emulator with a profiling infrastructure for transactional memory on FPGA
spellingShingle A multicore emulator with a profiling infrastructure for transactional memory on FPGA
Sönmez, Nehir
Simulació per ordinador
Gestió de memòria (Informàtica)
Àrees temàtiques de la UPC::Informàtica
title_short A multicore emulator with a profiling infrastructure for transactional memory on FPGA
title_full A multicore emulator with a profiling infrastructure for transactional memory on FPGA
title_fullStr A multicore emulator with a profiling infrastructure for transactional memory on FPGA
title_full_unstemmed A multicore emulator with a profiling infrastructure for transactional memory on FPGA
title_sort A multicore emulator with a profiling infrastructure for transactional memory on FPGA
dc.creator.none.fl_str_mv Sönmez, Nehir
author Sönmez, Nehir
author_facet Sönmez, Nehir
author_role author
dc.contributor.none.fl_str_mv Ünsal, Osman
Cristal Kestelman, Adrián
dc.subject.none.fl_str_mv Simulació per ordinador
Gestió de memòria (Informàtica)
Àrees temàtiques de la UPC::Informàtica
topic Simulació per ordinador
Gestió de memòria (Informàtica)
Àrees temàtiques de la UPC::Informàtica
description This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory multicore emulator with Hybrid Transactional Memory support, based on the Plasma open source soft processor core. We present the design and implementation of the TMbox system, which features an emulation system of up to 16 soft processor cores interconnected with a bi-directional ring bus, running at 50 MHz on a Virtex5-155t FPGA. Additionally, we build the first comprehensive infrastructure to profile Hybrid TM systems, an extensive visualization environment that enables examining complete transactional executions in detail. TMbox is a completely modifiable architecture implementing a multicore prototype with support for STM, HTM and Hybrid TM. It was written in various common design languages, and enables modifying the complete stack, down from the ISA, through the software toolchain, up to the well-optimized parallel code. With such an infrastructure, fast execution and quick performance evaluation can be made possible for studies in computer architecture.
publishDate 2012
dc.date.none.fl_str_mv 2012
2012-09-19
2017
2017-05-04
dc.type.none.fl_str_mv doctoral thesis
http://purl.org/coar/resource_type/c_db06
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/doctoralThesis
format doctoralThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/104207
https://dx.doi.org/10.5821/dissertation-2117-104207
url https://hdl.handle.net/2117/104207
https://dx.doi.org/10.5821/dissertation-2117-104207
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2

http://creativecommons.org/licenses/by-nc-sa/4.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2

http://creativecommons.org/licenses/by-nc-sa/4.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869423896979046400
score 15,300724

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