A multicore emulator with a profiling infrastructure for transactional memory on FPGA
This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory multicore emulator with Hybrid Transactional Memory support, based on the P...
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| Tipo de recurso: | tesis doctoral |
| Fecha de publicación: | 2012 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/104207 |
| Acceso en línea: | https://hdl.handle.net/2117/104207 https://dx.doi.org/10.5821/dissertation-2117-104207 |
| Access Level: | acceso abierto |
| Palabra clave: | Simulació per ordinador Gestió de memòria (Informàtica) Àrees temàtiques de la UPC::Informàtica |
| Sumario: | This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory multicore emulator with Hybrid Transactional Memory support, based on the Plasma open source soft processor core. We present the design and implementation of the TMbox system, which features an emulation system of up to 16 soft processor cores interconnected with a bi-directional ring bus, running at 50 MHz on a Virtex5-155t FPGA. Additionally, we build the first comprehensive infrastructure to profile Hybrid TM systems, an extensive visualization environment that enables examining complete transactional executions in detail. TMbox is a completely modifiable architecture implementing a multicore prototype with support for STM, HTM and Hybrid TM. It was written in various common design languages, and enables modifying the complete stack, down from the ISA, through the software toolchain, up to the well-optimized parallel code. With such an infrastructure, fast execution and quick performance evaluation can be made possible for studies in computer architecture. |
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