The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements
A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which current...
| Authors: | , |
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| Format: | article |
| Status: | Published version |
| Publication Date: | 2014 |
| Country: | España |
| Institution: | Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya) |
| Repository: | Recercat. Dipósit de la Recerca de Catalunya |
| OAI Identifier: | oai:recercat.cat:2445/55245 |
| Online Access: | https://hdl.handle.net/2445/55245 |
| Access Level: | Open access |
| Keyword: | Arquitectura d'ordinadors Funcions el·líptiques Integrals Computer architecture Elliptic functions |
| Summary: | A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular. |
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