Vitruvius+: An area-efficient RISC-V decoupled vector coprocessor for high performance computing applications

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article...

Descripción completa

Detalles Bibliográficos
Autores: Minervini Minervini, Francesco, Palomar Pérez, Óscar|||0000-0001-6729-4187, Unsal, Osman Sabri, Reggiani, Enrico, Quiroga Esparza, Josué Vladimir, Marimon Illana, Joan, Rojas Morales, Carlos|||0000-0002-7714-0277, Figueras Bagué, Roger, Ruíz Ramírez, Abraham Josafat, González Trejo, Alberto, Mendoza Escobar, Jonnatan, Vargas Valdivieso, Ivan|||0000-0002-5092-3829, Hernández Calderón, César Alejandro, Cabre Olive, Joan, Khoirunisya, Lina, Bouhali, Mustapha, Pavón Rivera, Julián, Moll Echeto, Francisco de Borja|||0000-0002-1290-3253, Olivieri, Mauro, Kovac, Mario, Kovac, Mate, Dragic, Leon, Valero Cortés, Mateo|||0000-0003-2917-2482, Cristal Kestelman, Adrián|||0000-0003-1277-9296
Tipo de recurso: artículo
Fecha de publicación:2023
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/384848
Acceso en línea:https://hdl.handle.net/2117/384848
https://dx.doi.org/10.1145/3575861
Access Level:acceso abierto
Palabra clave:Vector processing (Computer science)
High performance computing
Energy consumption
RISC-V
Vector accelerator
SIMD
HPC
Tractament vectorial
Càlcul intensiu (Informàtica)
Energia -- Consum
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Descripción
Sumario:The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article,1 we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm2 and maximum estimated power of ~920 mW for one instance of Vitruvius+ equipped with eight vector lanes.

Similares en LA Referencia