Implementing and evaluating graph algorithms for long vector architectures
High-Performance Computing can be accelerated using long-vector architectures. However, creating efficient coding implementations for these architectures can be challenging. This Master's thesis focuses on implementing four well-known and widely-used graph processing algorithms using the RISC-V...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2023 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/390659 |
| Acceso en línea: | https://hdl.handle.net/2117/390659 |
| Access Level: | acceso abierto |
| Palabra clave: | Graph algorithms High performance computing Computació vectors extensió vectorial grafs algoritme SIMD BFS PR CC SSSP ILA FPGA EPI RISC-V VPU implementació optimització evaluació anàlisi paraver extrae experimental codesign BSC Computation vector extension graphs algorithm Breadth First Search PageRank Connected Components Single Source Shortest Path implementation optimization evaluation analysis Algorismes de grafs Càlcul intensiu (Informàtica) Àrees temàtiques de la UPC::Informàtica::Enginyeria del software |
| Sumario: | High-Performance Computing can be accelerated using long-vector architectures. However, creating efficient coding implementations for these architectures can be challenging. This Master's thesis focuses on implementing four well-known and widely-used graph processing algorithms using the RISC-V Vector Extension, leveraging an experimental system in an FPGA. I present a graph storage format that benefits from long vectors and describe how these four algorithms can be rewritten to utilize it. This thesis also introduces an instrumentation tool for FPGA that I developed to link the output of electrical engineering software with performance analysis tools for HPC. This tool allows users to visualize information coming from the logic analyzer internal to the FPGA with powerful visualization tools, permitting fine-grain analysis of the FPGA signals correlated with the code running on it. This tool has been integrated into the experimental performance analysis tools of BSC. In this thesis I leverage this tool to analyze and improve my implementations of graph algorithms for long-vector architectures, collecting the process and thoughts behind each optimization. Finally, I compare the performance of my vector implementations with other machines, such as the NEC SX-Aurora, a commercial RISC-V board, and an Intel chip. |
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