Power and Speed Evaluation of Hyper-FET Circuits

Many emerging devices are currently being explored as potential alternatives to complementary metal–oxide–semiconductor technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at the circuit level. In...

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Detalhes bibliográficos
Autores: Núñez Martínez, Juan, Avedillo de Juan, María José
Formato: artículo
Estado:Versión publicada
Fecha de publicación:2019
País:España
Recursos:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/95124
Acesso em linha:https://hdl.handle.net/11441/95124
Access Level:acceso abierto
Palavra-chave:Hyper-FET
Low voltage
Low power
Phase transition materials
Steep subthreshold slope
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spelling Power and Speed Evaluation of Hyper-FET CircuitsNúñez Martínez, JuanAvedillo de Juan, María JoséHyper-FETLow voltageLow powerPhase transition materialsSteep subthreshold slopeMany emerging devices are currently being explored as potential alternatives to complementary metal–oxide–semiconductor technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at the circuit level. In this paper, we investigate the speed and power performance of hyper-field-effect transistor (Hyper-FET) circuits, comparing them with both high-performance and low standby power fin-shaped FET designs on the same technology node. The evaluation, which was carried out at the gate level and circuit level, includes a characterization of 8-bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from the transistor- and gate-level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated, which support the obtained results.Ministerio de Economía y Competitividad TEC2017-87052-PElectrónica y ElectromagnetismoMinisterio de Economía y Competitividad (MINECO). España2019info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/95124reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIEEE Access, 7, 6724-6732.TEC2017-87052-Pinfo:eu-repo/semantics/openAccessoai:idus.us.es:11441/951242026-06-17T12:51:07Z
dc.title.none.fl_str_mv Power and Speed Evaluation of Hyper-FET Circuits
title Power and Speed Evaluation of Hyper-FET Circuits
spellingShingle Power and Speed Evaluation of Hyper-FET Circuits
Núñez Martínez, Juan
Hyper-FET
Low voltage
Low power
Phase transition materials
Steep subthreshold slope
title_short Power and Speed Evaluation of Hyper-FET Circuits
title_full Power and Speed Evaluation of Hyper-FET Circuits
title_fullStr Power and Speed Evaluation of Hyper-FET Circuits
title_full_unstemmed Power and Speed Evaluation of Hyper-FET Circuits
title_sort Power and Speed Evaluation of Hyper-FET Circuits
dc.creator.none.fl_str_mv Núñez Martínez, Juan
Avedillo de Juan, María José
author Núñez Martínez, Juan
author_facet Núñez Martínez, Juan
Avedillo de Juan, María José
author_role author
author2 Avedillo de Juan, María José
author2_role author
dc.contributor.none.fl_str_mv Electrónica y Electromagnetismo
Ministerio de Economía y Competitividad (MINECO). España
dc.subject.none.fl_str_mv Hyper-FET
Low voltage
Low power
Phase transition materials
Steep subthreshold slope
topic Hyper-FET
Low voltage
Low power
Phase transition materials
Steep subthreshold slope
description Many emerging devices are currently being explored as potential alternatives to complementary metal–oxide–semiconductor technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at the circuit level. In this paper, we investigate the speed and power performance of hyper-field-effect transistor (Hyper-FET) circuits, comparing them with both high-performance and low standby power fin-shaped FET designs on the same technology node. The evaluation, which was carried out at the gate level and circuit level, includes a characterization of 8-bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from the transistor- and gate-level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated, which support the obtained results.
publishDate 2019
dc.date.none.fl_str_mv 2019
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/95124
url https://hdl.handle.net/11441/95124
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv IEEE Access, 7, 6724-6732.
TEC2017-87052-P
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300719

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