Flexible setup for the measurement of CMOS time-dependent variability with array-based integrated circuits

This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come wit...

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Detalles Bibliográficos
Autores: Nafria, Montserrat|||0000-0002-9549-2890, Martin Martinez, Javier|||0000-0001-5938-5898, Rodríguez Martínez, Rosana|||0000-0002-4565-6703, Diaz-Fortuny, Javier|||0000-0002-8186-071X, Saraza-Canflanca, Pablo|||0000-0003-2155-8305, Castro-Lopez, Rafael|||0000-0002-6247-3124, Roca, Elisenda|||0000-0001-6260-6495, Fernandez, Francisco V.|||0000-0001-8682-2280
Tipo de recurso: artículo
Fecha de publicación:2020
País:España
Institución:Universitat Autònoma de Barcelona
Repositorio:Dipòsit Digital de Documents de la UAB
Idioma:inglés
OAI Identifier:oai:ddd.uab.cat:248833
Acceso en línea:https://ddd.uab.cat/record/248833
https://dx.doi.org/urn:doi:10.1109/TIM.2019.2906415
Access Level:acceso abierto
Palabra clave:Transistors
Stress
Temperature measurement
Integrated circuits
Threshold voltage
Stress measurement
Human computer interaction
Descripción
Sumario:This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically time-consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals.

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