A Real-Time Error Detection (RTD) architecture and its use for reliability and post-silicon validation for F/F based memory arrays
This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error-detection and, thus, it can speed-up the access-time of arrays t...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2022 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/384274 |
| Acceso en línea: | https://hdl.handle.net/2117/384274 https://dx.doi.org/10.1109/TETC.2022.3141486 |
| Access Level: | acceso abierto |
| Palabra clave: | Integrated circuits -- Reliability Fault-tolerant computing Reliability Testing and fault-tolerance Memory design Error-checking Circuits integrats -- Fiabilitat Tolerància als errors (Informàtica) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error-detection and, thus, it can speed-up the access-time of arrays that use in-line error-correction. The approach can also reduce the time needed to root-cause array related bugs during post-silicon validation and product testing. The paper introduces a two-dimensional error-correction scheme based on RTD and, also, presents a proactive error-correction method that combines RTD with demand-scrubbing. The work describes how to build RTD into a memory array with flip-flops to track in real-time the column-parity. A comparison of the proposed two-dimensional ECC scheme, as compared to single-error-correction-double-error-detection, shows that the RTD design has comparable error-detection-and-correction strength and, depending on the array dimensions and configuration, RTD reduces access time by 4% to 26% at an area and power overhead (negative is a reduction) between -7% to 33% and -42% to 86% respectively. |
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