Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system

Detalhes bibliográficos
Autores: Barrera López de Turiso, Eduardo|||0000-0001-7197-8821, Astrain Etxezarreta, Miguel|||0000-0003-3486-0941, Prieto, Ignacio, Ruiz González, Mariano|||0000-0002-1337-0110, Fernández Hernando, Juan Luis, Pedica, Riccardo, Barcala, José María, Oller, Juan Carlos, Afif, Mehdi
Formato: artículo
Fecha de publicación:2018
País:España
Recursos:Universidad Politécnica de Madrid
Repositorio:Archivo Digital UPM
OAI Identifier:oai:oa.upm.es:78703
Acesso em linha:https://oa.upm.es/78703/
Access Level:acceso abierto
Palavra-chave:Interlock
FPGA
CompactRIO
IEC-61508
Reliability
Availability
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spelling Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection systemBarrera López de Turiso, Eduardo|||0000-0001-7197-8821Astrain Etxezarreta, Miguel|||0000-0003-3486-0941Prieto, IgnacioRuiz González, Mariano|||0000-0002-1337-0110Fernández Hernando, Juan LuisPedica, RiccardoBarcala, José MaríaOller, Juan CarlosAfif, MehdiInterlockFPGACompactRIOIEC-61508ReliabilityAvailability20182018-02-01journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articlehttps://oa.upm.es/78703/reponame:Archivo Digital UPMinstname:Universidad Politécnica de MadridInglésenopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:oa.upm.es:787032026-06-21T12:45:07Z
dc.title.none.fl_str_mv Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system
title Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system
spellingShingle Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system
Barrera López de Turiso, Eduardo|||0000-0001-7197-8821
Interlock
FPGA
CompactRIO
IEC-61508
Reliability
Availability
title_short Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system
title_full Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system
title_fullStr Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system
title_full_unstemmed Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system
title_sort Methodology for the deployment of ITER Fast Plant Interlock system. Use case: ITER Poloidal Field and Central Solenoid coil's power converter protection system
dc.creator.none.fl_str_mv Barrera López de Turiso, Eduardo|||0000-0001-7197-8821
Astrain Etxezarreta, Miguel|||0000-0003-3486-0941
Prieto, Ignacio
Ruiz González, Mariano|||0000-0002-1337-0110
Fernández Hernando, Juan Luis
Pedica, Riccardo
Barcala, José María
Oller, Juan Carlos
Afif, Mehdi
author Barrera López de Turiso, Eduardo|||0000-0001-7197-8821
author_facet Barrera López de Turiso, Eduardo|||0000-0001-7197-8821
Astrain Etxezarreta, Miguel|||0000-0003-3486-0941
Prieto, Ignacio
Ruiz González, Mariano|||0000-0002-1337-0110
Fernández Hernando, Juan Luis
Pedica, Riccardo
Barcala, José María
Oller, Juan Carlos
Afif, Mehdi
author_role author
author2 Astrain Etxezarreta, Miguel|||0000-0003-3486-0941
Prieto, Ignacio
Ruiz González, Mariano|||0000-0002-1337-0110
Fernández Hernando, Juan Luis
Pedica, Riccardo
Barcala, José María
Oller, Juan Carlos
Afif, Mehdi
author2_role author
author
author
author
author
author
author
author
dc.subject.none.fl_str_mv Interlock
FPGA
CompactRIO
IEC-61508
Reliability
Availability
topic Interlock
FPGA
CompactRIO
IEC-61508
Reliability
Availability
publishDate 2018
dc.date.none.fl_str_mv 2018
2018-02-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://oa.upm.es/78703/
url https://oa.upm.es/78703/
dc.language.none.fl_str_mv Inglés
en
language_invalid_str_mv Inglés
en
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv reponame:Archivo Digital UPM
instname:Universidad Politécnica de Madrid
instname_str Universidad Politécnica de Madrid
reponame_str Archivo Digital UPM
collection Archivo Digital UPM
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,812429

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