Architectural support for real-time task scheduling in SMT processors

In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. However, since threads share many resources, like caches, they also interfere...

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Autores: Cazorla Almeida, Francisco Javier, Knijnenburg, Peter M.W., Sakellariou, Rizos, Fernández, Enrique, Ramírez Bellido, Alejandro, Valero Cortés, Mateo|||0000-0003-2917-2482
Tipo de recurso: informe técnico
Fecha de publicación:2005
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/106650
Acceso en línea:https://hdl.handle.net/2117/106650
Access Level:acceso abierto
Palabra clave:Embedded computer systems
Real-time data processing
Simultaneous multithreading processors
SMT
Resource allocation
Real time scheduling
Predictable performance
Ordinadors immersos, Sistemes d'
Temps real (Informàtica)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
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spelling Architectural support for real-time task scheduling in SMT processorsCazorla Almeida, Francisco JavierKnijnenburg, Peter M.W.Sakellariou, RizosFernández, EnriqueRamírez Bellido, AlejandroValero Cortés, Mateo|||0000-0003-2917-2482Embedded computer systemsReal-time data processingSimultaneous multithreading processorsSMTResource allocationReal time schedulingPredictable performanceOrdinadors immersos, Sistemes d'Temps real (Informàtica)Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadorsIn Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. However, since threads share many resources, like caches, they also interfere with each other. As a result, execution times of applications become highly unpredictable and highly dependent on the context in which an application is executed. Obviously, this poses problems if an SMT is to be used in a (soft) real time system. In this paper, we propose two novel hardware mechanisms that can be used to reduce this performance variability. In contrast to previous approaches, our proposed mechanisms do not need any information beyond the information already known by traditional job schedulers. Neither do they require extensive profiling of workloads to determine optimal schedules. Our mechanisms are based on dynamic resource partitioning. The OS level job scheduler needs to be slightly adapted in order to provide the hardware resource allocator some information on how this resource partitioning needs to be done. We show that our mechanisms provide high stability for SMT architectures to be used in real time systems: the real time benchmarks we used meet their deadlines in more than 98% of the cases considered while the other thread in the workload still achieves high throughput.20052005-01-0120172017-07-20reporthttp://purl.org/coar/resource_type/c_93fcVoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/reportapplication/pdfhttps://hdl.handle.net/2117/106650reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/1066502026-05-27T15:37:01Z
dc.title.none.fl_str_mv Architectural support for real-time task scheduling in SMT processors
title Architectural support for real-time task scheduling in SMT processors
spellingShingle Architectural support for real-time task scheduling in SMT processors
Cazorla Almeida, Francisco Javier
Embedded computer systems
Real-time data processing
Simultaneous multithreading processors
SMT
Resource allocation
Real time scheduling
Predictable performance
Ordinadors immersos, Sistemes d'
Temps real (Informàtica)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
title_short Architectural support for real-time task scheduling in SMT processors
title_full Architectural support for real-time task scheduling in SMT processors
title_fullStr Architectural support for real-time task scheduling in SMT processors
title_full_unstemmed Architectural support for real-time task scheduling in SMT processors
title_sort Architectural support for real-time task scheduling in SMT processors
dc.creator.none.fl_str_mv Cazorla Almeida, Francisco Javier
Knijnenburg, Peter M.W.
Sakellariou, Rizos
Fernández, Enrique
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author Cazorla Almeida, Francisco Javier
author_facet Cazorla Almeida, Francisco Javier
Knijnenburg, Peter M.W.
Sakellariou, Rizos
Fernández, Enrique
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author_role author
author2 Knijnenburg, Peter M.W.
Sakellariou, Rizos
Fernández, Enrique
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author2_role author
author
author
author
author
dc.subject.none.fl_str_mv Embedded computer systems
Real-time data processing
Simultaneous multithreading processors
SMT
Resource allocation
Real time scheduling
Predictable performance
Ordinadors immersos, Sistemes d'
Temps real (Informàtica)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
topic Embedded computer systems
Real-time data processing
Simultaneous multithreading processors
SMT
Resource allocation
Real time scheduling
Predictable performance
Ordinadors immersos, Sistemes d'
Temps real (Informàtica)
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
description In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. However, since threads share many resources, like caches, they also interfere with each other. As a result, execution times of applications become highly unpredictable and highly dependent on the context in which an application is executed. Obviously, this poses problems if an SMT is to be used in a (soft) real time system. In this paper, we propose two novel hardware mechanisms that can be used to reduce this performance variability. In contrast to previous approaches, our proposed mechanisms do not need any information beyond the information already known by traditional job schedulers. Neither do they require extensive profiling of workloads to determine optimal schedules. Our mechanisms are based on dynamic resource partitioning. The OS level job scheduler needs to be slightly adapted in order to provide the hardware resource allocator some information on how this resource partitioning needs to be done. We show that our mechanisms provide high stability for SMT architectures to be used in real time systems: the real time benchmarks we used meet their deadlines in more than 98% of the cases considered while the other thread in the workload still achieves high throughput.
publishDate 2005
dc.date.none.fl_str_mv 2005
2005-01-01
2017
2017-07-20
dc.type.none.fl_str_mv report
http://purl.org/coar/resource_type/c_93fc
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/report
format report
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/106650
url https://hdl.handle.net/2117/106650
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869419290645495808
score 15,300724

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