Fitting processor architectures for measurement-based probabilistic timing analysis
The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case execution time (WCET) analysis of software programs - which is often required, esp...
| Autores: | , , , , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2016 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/100471 |
| Acceso en línea: | https://hdl.handle.net/2117/100471 https://dx.doi.org/10.1016/j.micpro.2016.07.014 |
| Access Level: | acceso abierto |
| Palabra clave: | Embedded computer systems Cache memory Real-time data processing Worst-case execution time Processor architecture Cache memories Probabilistic analysis Time randomization Ordinadors immersos, Sistemes d' Memòria cau Temps real (Informàtica) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case execution time (WCET) analysis of software programs - which is often required, especially for programs at the highest levels of integrity - an even harder challenge. State-of-the-art WCET analysis techniques are hampered by the soaring cost and complexity of obtaining accurate knowledge of the internal operation of advanced processors and the difficulty of relating data obtained from measurement observations with reliable worst-case behaviour. This frustrating conundrum calls for novel solutions, with low intrusiveness on development practice. Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques offer the opportunity to simultaneously reduce the cost of acquiring the knowledge needed for computing reliable WCET bounds and gain increased confidence in the representativeness of measurement observations. This paper describes the changes required in the design of several high-performance features - massively used in modern processors - to meet MBPTA requirements. |
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