Optimization of FinFET-based gain cells for low power sub-vt embedded drams
Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to achieve the maximum cell performance (i.e., retention time, access time, and energ...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2018 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/122302 |
| Acceso en línea: | https://hdl.handle.net/2117/122302 |
| Access Level: | acceso abierto |
| Palabra clave: | Power electronics SRAM DRAM gain-cells FinFET Electrònica de potència Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
| Sumario: | Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to achieve the maximum cell performance (i.e., retention time, access time, and energy consumption) suitable for the sub-V T operating level. In this work, we show that asymmetrically resizing the memory cell (i.e., the channel length of the write access transistor and the width of the rest of the devices) results in a 3.5× increase in retention time when compared to the nominal case while reducing area, as well. In terms of reliability (e.g., variability and soft errors), the resizing also improves the cell robustness (50% and 1.9×, respectively) when the cells are operated at sub-V T level. |
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