Decomposition and technology mapping of speed-independent circuits using Boolean relations

This paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed method iteratively performs Boolean deco...

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Detalhes bibliográficos
Autores: Cortadella, Jordi|||0000-0001-8114-250X, Kishinevsky, Michael, Kondratyev, Alex, Lavagno, Luciano, Pastor Llorens, Enric|||0000-0002-7587-8702, Yakovlev, Alex
Formato: artículo
Fecha de publicación:1999
País:España
Recursos:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/126063
Acesso em linha:https://hdl.handle.net/2117/126063
https://dx.doi.org/10.1109/43.784116
Access Level:acceso abierto
Palavra-chave:Asynchronous circuits
Logic circuits
Logic design
Boolean relations (BR’s)
Logic decomposition
Speed independence
Technology mapping
Circuits asíncrons
Circuits lògics
Estructura lògica
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
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repository_id_str
spelling Decomposition and technology mapping of speed-independent circuits using Boolean relationsCortadella, Jordi|||0000-0001-8114-250XKishinevsky, MichaelKondratyev, AlexLavagno, LucianoPastor Llorens, Enric|||0000-0002-7587-8702Yakovlev, AlexAsynchronous circuitsLogic circuitsLogic designBoolean relations (BR’s)Logic decompositionSpeed independenceTechnology mappingCircuits asíncronsCircuits lògicsEstructura lògicaÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integratsThis paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed method iteratively performs Boolean decomposition of each such gate F into a two-input combinational or sequential gate G available in the library and two gates H/sub 1/ and H/sub 2/ simpler than F, while preserving the original behavior and speed-independence of the circuit. To extract functions for H/sub 1/ and H/sub 2/ the method uses Boolean relations as opposed to the less powerful algebraic factorization approach used in previous methods. After logic decomposition, the overall library matching and optimization is carried out. Logic resynthesis, performed after speed-independent signal insertion for H/sub 1/ and H/sub 2/, allows for sharing of decomposed logic. Overall, this method is more general than the existing techniques based on restricted decomposition architectures, and thereby leads to better results in technology mapping.Peer Reviewed19991999-09-0120182018-12-20journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/126063https://dx.doi.org/10.1109/43.784116reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/1260632026-05-27T15:37:01Z
dc.title.none.fl_str_mv Decomposition and technology mapping of speed-independent circuits using Boolean relations
title Decomposition and technology mapping of speed-independent circuits using Boolean relations
spellingShingle Decomposition and technology mapping of speed-independent circuits using Boolean relations
Cortadella, Jordi|||0000-0001-8114-250X
Asynchronous circuits
Logic circuits
Logic design
Boolean relations (BR’s)
Logic decomposition
Speed independence
Technology mapping
Circuits asíncrons
Circuits lògics
Estructura lògica
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
title_short Decomposition and technology mapping of speed-independent circuits using Boolean relations
title_full Decomposition and technology mapping of speed-independent circuits using Boolean relations
title_fullStr Decomposition and technology mapping of speed-independent circuits using Boolean relations
title_full_unstemmed Decomposition and technology mapping of speed-independent circuits using Boolean relations
title_sort Decomposition and technology mapping of speed-independent circuits using Boolean relations
dc.creator.none.fl_str_mv Cortadella, Jordi|||0000-0001-8114-250X
Kishinevsky, Michael
Kondratyev, Alex
Lavagno, Luciano
Pastor Llorens, Enric|||0000-0002-7587-8702
Yakovlev, Alex
author Cortadella, Jordi|||0000-0001-8114-250X
author_facet Cortadella, Jordi|||0000-0001-8114-250X
Kishinevsky, Michael
Kondratyev, Alex
Lavagno, Luciano
Pastor Llorens, Enric|||0000-0002-7587-8702
Yakovlev, Alex
author_role author
author2 Kishinevsky, Michael
Kondratyev, Alex
Lavagno, Luciano
Pastor Llorens, Enric|||0000-0002-7587-8702
Yakovlev, Alex
author2_role author
author
author
author
author
dc.subject.none.fl_str_mv Asynchronous circuits
Logic circuits
Logic design
Boolean relations (BR’s)
Logic decomposition
Speed independence
Technology mapping
Circuits asíncrons
Circuits lògics
Estructura lògica
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
topic Asynchronous circuits
Logic circuits
Logic design
Boolean relations (BR’s)
Logic decomposition
Speed independence
Technology mapping
Circuits asíncrons
Circuits lògics
Estructura lògica
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
description This paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed method iteratively performs Boolean decomposition of each such gate F into a two-input combinational or sequential gate G available in the library and two gates H/sub 1/ and H/sub 2/ simpler than F, while preserving the original behavior and speed-independence of the circuit. To extract functions for H/sub 1/ and H/sub 2/ the method uses Boolean relations as opposed to the less powerful algebraic factorization approach used in previous methods. After logic decomposition, the overall library matching and optimization is carried out. Logic resynthesis, performed after speed-independent signal insertion for H/sub 1/ and H/sub 2/, allows for sharing of decomposed logic. Overall, this method is more general than the existing techniques based on restricted decomposition architectures, and thereby leads to better results in technology mapping.
publishDate 1999
dc.date.none.fl_str_mv 1999
1999-09-01
2018
2018-12-20
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/126063
https://dx.doi.org/10.1109/43.784116
url https://hdl.handle.net/2117/126063
https://dx.doi.org/10.1109/43.784116
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869418730358833152
score 15,198674

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