Lazy transition systems and asynchronous circuits synthesis with relative timing assumptions
This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a tran...
| Autores: | , , , , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2002 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/126134 |
| Acceso en línea: | https://hdl.handle.net/2117/126134 https://dx.doi.org/10.1109/43.980253 |
| Access Level: | acceso abierto |
| Palabra clave: | Asynchronous circuits Integrated circuits Logic design Lazy transition systems Logic synthesis Relative timing Circuits asíncrons Circuits integrats Estructura lògica Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Sumario: | This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. Lazy transition systems can be effectively used to model the behavior of asynchronous circuits in which relative timing assumptions can be made on the occurrence of events. These assumptions can be derived from the information known a priori about the delay of the environment and the timing characteristics of the gates that will implement the circuit. The paper presents the necessary conditions to generate circuits and a synthesis algorithm that exploits the timing assumptions for optimization. It also proposes a method for back-annotation that derives a set of sufficient timing constraints that guarantee the correctness of the circuit. |
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