Design, implementation, and testing of a High-Resolution Timer for motor control and power applications
Microcontroller designing allows companies to launch flexible and complex product implementations that can target a wide variety of industrial applications. Monolithic Power Systems, INC. is developing its own product to cover the power converters and motor control sector. Among the many submodules...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2023 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/389286 |
| Acceso en línea: | https://hdl.handle.net/2117/389286 |
| Access Level: | acceso embargado |
| Palabra clave: | Automatic timers Digital-to-analog converters MCU timer counter digital design VHDL power converter motor control high-resolution RTL implementation testing simulations Temporitzadors Convertidors digital/analògics Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
| Sumario: | Microcontroller designing allows companies to launch flexible and complex product implementations that can target a wide variety of industrial applications. Monolithic Power Systems, INC. is developing its own product to cover the power converters and motor control sector. Among the many submodules that can be found inside the MCU, the master thesis focuses its work on the digital design and RTL implementation of a high-resolution timer with a maximum accuracy of 200 ps in the period and the generated PWM duty cycle. The result is a ~10 um2 peripheral able to generate complex waveform configurations, receive external signals for closed-loop output control, and generate the necessary triggers for other peripherals inside the MCU. An organized register map is also generated to allow the user to set-up and monitor the state of the IP. It supports many topologies including buck, boost, full bridge phase shifted converters, either in voltage or current mode, as well as motor applications with deadtime insertion and overlap protection, among all the possible waveform modification techniques. To meet the timing requirements, the timer uses a PLL clock of 156.25 MHz and 32 phases along with state-of-the-art technology to delay the duty cycle and period edges with precision by clock switching the signals over the PLL phases. This paper, gathers all the information found about the possible applications and market solutions to present the final design with all the features rigorously explained. Finally, several tests are performed to check its behavior and extract conclusions. |
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